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Searched refs:cfg (Results 1 – 25 of 40) sorted by relevance

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/optee_os-3.20.0/core/drivers/
A Dstpmic1.c738 cfg->mask = mask; in stpmic1_bo_voltage_cfg()
752 if ((value & cfg->mask) >= cfg->min_value) in stpmic1_bo_voltage_unpg()
755 return stpmic1_register_update(cfg->ctrl_reg, cfg->min_value, in stpmic1_bo_voltage_unpg()
756 cfg->mask); in stpmic1_bo_voltage_unpg()
777 assert(cfg->pd_reg); in stpmic1_bo_pull_down_unpg()
779 return stpmic1_register_update(cfg->pd_reg, cfg->pd_value, in stpmic1_bo_pull_down_unpg()
803 return stpmic1_register_update(cfg->mrst_reg, cfg->mrst_value, in stpmic1_bo_mask_reset_unpg()
867 assert(cfg->lp_reg); in stpmic1_lp_load_unpg()
946 cfg->mask = mask; in stpmic1_lp_voltage_cfg()
953 assert(cfg->lp_reg); in stpmic1_lp_voltage_unpg()
[all …]
A Dversal_nvm.c273 req.ibuf[0].buf = &cfg; in versal_efuse_read_user_data()
406 memcpy(&cfg, keys, sizeof(cfg)); in versal_efuse_write_aes_keys()
425 memcpy(&cfg, hash, sizeof(cfg)); in versal_efuse_write_ppk_hash()
444 memcpy(&cfg, p, sizeof(cfg)); in versal_efuse_write_iv()
463 memcpy(&cfg, p, sizeof(cfg)); in versal_efuse_write_dec_only()
482 memcpy(&cfg, p, sizeof(cfg)); in versal_efuse_write_sec()
501 memcpy(&cfg, p, sizeof(cfg)); in versal_efuse_write_misc()
520 memcpy(&cfg, p, sizeof(cfg)); in versal_efuse_write_glitch_cfg()
540 memcpy(&cfg, p, sizeof(cfg)); in versal_efuse_write_boot_env()
559 memcpy(&cfg, p, sizeof(cfg)); in versal_efuse_write_sec_misc1()
[all …]
A Datmel_shdwc.c26 #define SHDW_WK_PIN(reg, cfg) ((reg) & \ argument
27 AT91_SHDW_WKUPIS((cfg)->wkup_pin_input))
28 #define SHDW_RTCWK(reg, cfg) (((reg) >> ((cfg)->sr_rtcwk_shift)) & 0x1) argument
29 #define SHDW_RTTWK(reg, cfg) (((reg) >> ((cfg)->sr_rttwk_shift)) & 0x1) argument
30 #define SHDW_RTCWKEN(cfg) BIT((cfg)->mr_rtcwk_shift) argument
31 #define SHDW_RTTWKEN(cfg) BIT((cfg)->mr_rttwk_shift) argument
A Dtzc400.c267 assert(tzc.base && cfg); in tzc_configure_region()
270 assert(((cfg->filters >> tzc.num_filters) == 0) && in tzc_configure_region()
278 assert(((cfg->top <= (UINT64_MAX >> (64 - tzc.addr_width))) && in tzc_configure_region()
279 (cfg->base < cfg->top))); in tzc_configure_region()
282 assert(((cfg->base | (cfg->top + 1)) & (4096 - 1)) == 0); in tzc_configure_region()
284 assert(cfg->sec_attr <= TZC_REGION_S_RDWR); in tzc_configure_region()
294 tzc_write_region_top_low(tzc.base, region, addr_low(cfg->top)); in tzc_configure_region()
299 (cfg->sec_attr << REG_ATTR_SEC_SHIFT) | in tzc_configure_region()
300 cfg->filters); in tzc_configure_region()
324 cfg->sec_attr = val32 >> REG_ATTR_SEC_SHIFT; in tzc_get_region_config()
[all …]
A Dstm32_gpio.c68 cfg->mode = (io_read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) & in get_gpio_cfg()
71 cfg->otype = (io_read32(base + GPIO_OTYPER_OFFSET) >> pin) & 1; in get_gpio_cfg()
76 cfg->pupd = (io_read32(base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & in get_gpio_cfg()
79 cfg->od = (io_read32(base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; in get_gpio_cfg()
82 cfg->af = (io_read32(base + GPIO_AFRL_OFFSET) >> (pin << 2)) & in get_gpio_cfg()
85 cfg->af = (io_read32(base + GPIO_AFRH_OFFSET) >> in get_gpio_cfg()
104 cfg->mode << (pin << 1)); in set_gpio_cfg()
112 cfg->ospeed << (pin << 1)); in set_gpio_cfg()
116 cfg->pupd << (pin << 1)); in set_gpio_cfg()
122 cfg->af << (pin << 2)); in set_gpio_cfg()
[all …]
A Dversal_puf.c98 struct versal_puf_cfg *cfg) in versal_puf_register() argument
136 req.global_var_filter = cfg->global_var_filter; in versal_puf_register()
137 req.shutter_value = cfg->shutter_value; in versal_puf_register()
138 req.puf_operation = cfg->puf_operation; in versal_puf_register()
139 req.read_option = cfg->read_option; in versal_puf_register()
140 req.reg_mode = cfg->reg_mode; in versal_puf_register()
178 struct versal_puf_cfg *cfg) in versal_puf_regenerate() argument
217 req.shutter_value = cfg->shutter_value; in versal_puf_regenerate()
218 req.puf_operation = cfg->puf_operation; in versal_puf_regenerate()
219 req.read_option = cfg->read_option; in versal_puf_regenerate()
[all …]
A Dversal_trng.c208 struct trng_cfg cfg; member
513 trng_write32(trng->cfg.addr, off, 0); in trng_write32_range()
522 trng_write32(trng->cfg.addr, off, val); in trng_write32_range()
561 trng_clrset32(trng->cfg.addr, TRNG_CTRL, in trng_hold_reset()
595 trng_clrset32(trng->cfg.addr, TRNG_CTRL, in trng_collect_random()
744 trng_write32(trng->cfg.addr, TRNG_CTRL, in trng_reseed_internal()
1065 .cfg.base = TRNG_BASE,
1066 .cfg.len = TRNG_SIZE,
1119 versal_trng.cfg.base, in trng_hrng_mode_init()
1120 versal_trng.cfg.len); in trng_hrng_mode_init()
[all …]
A Dstm32_i2c.c322 cfg->cr1 = io_read32(base + I2C_CR1); in save_cfg()
323 cfg->cr2 = io_read32(base + I2C_CR2); in save_cfg()
324 cfg->oar1 = io_read32(base + I2C_OAR1); in save_cfg()
325 cfg->oar2 = io_read32(base + I2C_OAR2); in save_cfg()
339 io_write32(base + I2C_OAR1, cfg->oar1); in restore_cfg()
340 io_write32(base + I2C_CR2, cfg->cr2); in restore_cfg()
350 DMSG("CR1: %#"PRIx32, cfg->cr1); in dump_cfg()
351 DMSG("CR2: %#"PRIx32, cfg->cr2); in dump_cfg()
352 DMSG("OAR1: %#"PRIx32, cfg->oar1); in dump_cfg()
353 DMSG("OAR2: %#"PRIx32, cfg->oar2); in dump_cfg()
[all …]
/optee_os-3.20.0/core/include/dt-bindings/dma/
A Dat91.h37 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) \ argument
38 (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
46 #define AT91_XDMAC_DT_GET_PER_IF(cfg) \ argument
47 (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
54 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ argument
/optee_os-3.20.0/core/include/drivers/
A Dstpmic1.h222 int stpmic1_bo_enable_unpg(struct stpmic1_bo_cfg *cfg);
224 struct stpmic1_bo_cfg *cfg);
225 int stpmic1_bo_voltage_unpg(struct stpmic1_bo_cfg *cfg);
228 struct stpmic1_bo_cfg *cfg);
229 int stpmic1_bo_pull_down_unpg(struct stpmic1_bo_cfg *cfg);
232 int stpmic1_bo_mask_reset_unpg(struct stpmic1_bo_cfg *cfg);
235 int stpmic1_lp_cfg(const char *name, struct stpmic1_lp_cfg *cfg);
236 int stpmic1_lp_load_unpg(struct stpmic1_lp_cfg *cfg);
238 int stpmic1_lp_mode_unpg(struct stpmic1_lp_cfg *cfg,
241 struct stpmic1_lp_cfg *cfg);
[all …]
A Dversal_puf.h72 struct versal_puf_cfg *cfg);
74 struct versal_puf_cfg *cfg);
/optee_os-3.20.0/core/arch/arm/plat-stm32mp1/drivers/
A Dstm32mp1_pmic.c90 struct stpmic1_bo_cfg cfg; member
189 struct stpmic1_lp_cfg cfg; member
207 struct regu_lp_config *cfg; member
246 state->cfg = realloc(state->cfg, in dt_get_regu_low_power_config()
248 if (!state->cfg) in dt_get_regu_low_power_config()
314 struct stpmic1_lp_cfg *cfg = &state->cfg[i].cfg; in stm32mp_pmic_apply_lp_config() local
317 stpmic1_lp_load_unpg(cfg)) in stm32mp_pmic_apply_lp_config()
321 stpmic1_lp_on_off_unpg(cfg, 1)) in stm32mp_pmic_apply_lp_config()
325 stpmic1_lp_on_off_unpg(cfg, 0)) in stm32mp_pmic_apply_lp_config()
329 stpmic1_lp_voltage_unpg(cfg)) in stm32mp_pmic_apply_lp_config()
[all …]
/optee_os-3.20.0/mk/
A Dcheckconf.mk68 define cfg-vars-by-prefix
81 define cfg-make-define
92 define cfg-cmake-set
101 cfg-one-enabled = $(if $(filter y, $(foreach var,$(1),$($(var)))),y,n)
106 cfg-all-enabled = $(if $(strip $(1)),$(if $(call _cfg-all-enabled,$(1)),y,n),n)
121 cfg-depends-all = \
124 $(if $(filter y,$(call cfg-all-enabled,$(2))), \
136 cfg-depends-one = \
139 $(if $(filter y,$(call cfg-one-enabled,$(2))), \
152 cfg-enable-all-depends = \
[all …]
A Dconfig.mk163 $(eval $(call cfg-depends-all,CFG_REE_FS_INTEGRITY_RPMB,CFG_RPMB_FS))
586 $(call cfg-check-value,FTRACE_BUF_WHEN_FULL,shift stop wrap)
600 $(call cfg-depends-all,CFG_SYSCALL_FTRACE,CFG_FTRACE_SUPPORT)
643 CFG_SECSTOR_TA_MGMT_PTA ?= $(call cfg-all-enabled,CFG_SECSTOR_TA)
650 $(eval $(call cfg-depends-all,CFG_SYSTEM_PTA,CFG_WITH_USER_TA))
900 $(eval $(call cfg-depends-all,CFG_CORE_BTI,CFG_ARM64_core))
906 $(eval $(call cfg-depends-all,CFG_TA_BTI,CFG_ARM64_core))
921 $(eval $(call cfg-depends-all,CFG_MEMTAG,CFG_ARM64_core))
953 $(eval $(call cfg-depends-all,CFG_CORE_PAUTH,CFG_ARM64_core))
954 $(eval $(call cfg-depends-all,CFG_TA_PAUTH,CFG_ARM64_core))
[all …]
/optee_os-3.20.0/core/drivers/clk/
A Dclk-stm32-core.c321 return stm32_mux_get_parent(cfg->mux_id); in clk_stm32_mux_get_parent()
341 stm32_gate_enable(cfg->gate_id); in clk_stm32_gate_enable()
350 stm32_gate_disable(cfg->gate_id); in clk_stm32_gate_disable()
369 if (stm32_gate_rdy_disable(cfg->gate_id)) in clk_stm32_gate_ready_disable()
406 if (cfg->mux_id == NO_MUX) { in clk_stm32_composite_get_parent()
418 if (cfg->mux_id == NO_MUX) in clk_stm32_composite_set_parent()
429 if (cfg->div_id == NO_DIV) in clk_stm32_composite_get_rate()
440 if (cfg->div_id == NO_DIV) in clk_stm32_composite_set_rate()
450 stm32_gate_enable(cfg->gate_id); in clk_stm32_composite_gate_enable()
459 stm32_gate_disable(cfg->gate_id); in clk_stm32_composite_gate_disable()
[all …]
/optee_os-3.20.0/core/drivers/crypto/caam/
A Dsub.mk11 subdirs-$(call cfg-one-enabled, CFG_NXP_CAAM_HASH_DRV CFG_NXP_CAAM_HMAC_DRV) += hash
12 subdirs-$(call cfg-one-enabled, CFG_NXP_CAAM_CIPHER_DRV CFG_NXP_CAAM_CMAC_DRV) += cipher
/optee_os-3.20.0/core/
A Dcrypto.mk117 cryp-enable-all-depends = $(call cfg-enable-all-depends,$(strip $(1)),$(foreach v,$(2),CFG_CRYPTO_$…
123 cryp-dep-one = $(call cfg-depends-one,CFG_CRYPTO_$(strip $(1)),$(patsubst %, CFG_CRYPTO_%,$(strip $…
124 cryp-dep-all = $(call cfg-depends-all,CFG_CRYPTO_$(strip $(1)),$(patsubst %, CFG_CRYPTO_%,$(strip $…
200 _CFG_CORE_LTC_AES_DESC := $(call cfg-one-enabled, CFG_CRYPTO_XTS CFG_CRYPTO_CCM)
209 _CFG_CORE_LTC_SHA256_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA256_DESC \
212 _CFG_CORE_LTC_SHA384_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA384_DESC \
214 _CFG_CORE_LTC_SHA512_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA512_DESC \
217 _CFG_CORE_LTC_AES_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_AES_DESC \
233 ltc-one-enabled = $(call cfg-one-enabled,$(foreach v,$(1),_CFG_CORE_LTC_$(v)))
/optee_os-3.20.0/lib/libmbedtls/core/
A Dsub.mk3 srcs-$(call cfg-one-enabled, CFG_CRYPTO_MD5 CFG_CRYPTO_SHA1 CFG_CRYPTO_SHA224 \
24 srcs-$(call cfg-one-enabled, CFG_CRYPTO_RSA CFG_CRYPTO_DH \
/optee_os-3.20.0/core/lib/libtomcrypt/src/ciphers/
A Dsub.mk1 subdirs-$(call cfg-one-enabled, _CFG_CORE_LTC_AES _CFG_CORE_LTC_AES_DESC) += aes
/optee_os-3.20.0/core/arch/arm/kernel/
A Dlink_dummies_init.c17 struct core_mmu_config *cfg __unused) in core_init_mmu_map()
/optee_os-3.20.0/core/arch/arm/dts/
A Dstm32mp153.dtsi42 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
55 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
/optee_os-3.20.0/core/pta/tests/
A Dsub.mk1 srcs-$(call cfg-all-enabled,CFG_REE_FS CFG_WITH_USER_TA) += fs_htree.c
/optee_os-3.20.0/core/arch/arm/plat-stm32mp1/
A Dconf.mk69 ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n)
72 ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y)
169 ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP),y)
174 $(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL))
306 ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID))
314 ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y)
/optee_os-3.20.0/core/arch/arm/mm/
A Dcore_mmu_v7.c771 void core_init_mmu_regs(struct core_mmu_config *cfg) in core_init_mmu_regs() argument
773 cfg->ttbr = core_mmu_get_main_ttb_pa(&default_partition) | in core_init_mmu_regs()
776 cfg->prrr = ATTR_DEVICE_PRRR | ATTR_NORMAL_CACHED_PRRR | in core_init_mmu_regs()
778 cfg->nmrr = ATTR_DEVICE_NMRR | ATTR_NORMAL_CACHED_NMRR | in core_init_mmu_regs()
781 cfg->prrr |= PRRR_NS1 | PRRR_DS1; in core_init_mmu_regs()
788 cfg->dacr = DACR_DOMAIN(0, DACR_DOMAIN_PERM_CLIENT) | in core_init_mmu_regs()
795 cfg->ttbcr = TTBCR_N_VALUE; in core_init_mmu_regs()
A Dcore_mmu_lpae.c838 void core_init_mmu_regs(struct core_mmu_config *cfg) in core_init_mmu_regs() argument
843 cfg->ttbr0_base = virt_to_phys(base_xlation_table[0][0]); in core_init_mmu_regs()
844 cfg->ttbr0_core_offset = sizeof(base_xlation_table[0][0]); in core_init_mmu_regs()
855 cfg->mair0 = mair; in core_init_mmu_regs()
864 cfg->ttbcr = ttbcr; in core_init_mmu_regs()
905 void core_init_mmu_regs(struct core_mmu_config *cfg) in core_init_mmu_regs() argument
911 cfg->ttbr0_el1_base = virt_to_phys(base_xlation_table[0][0]); in core_init_mmu_regs()
912 cfg->ttbr0_core_offset = sizeof(base_xlation_table[0][0]); in core_init_mmu_regs()
927 cfg->mair_el1 = mair; in core_init_mmu_regs()
943 cfg->tcr_el1 = tcr; in core_init_mmu_regs()

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