/optee_os-3.20.0/core/arch/arm/dts/ |
A D | stm32mp131.dtsi | 42 #clock-cells = <0>; 43 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 compatible = "fixed-clock"; 54 #clock-cells = <0>; 56 clock-frequency = <32768>; 60 #clock-cells = <0>; 62 clock-frequency = <32000>; 66 #clock-cells = <0>; 72 #clock-cells = <0>; [all …]
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A D | sama5d2.dtsi | 36 clock-names = "cpu"; 50 clock-names = "apb_pclk"; 66 clock-names = "apb_pclk"; 85 #clock-cells = <0>; 86 clock-frequency = <0>; 91 #clock-cells = <0>; 92 clock-frequency = <0>; 251 #clock-cells = <0>; 286 #clock-cells = <2>; 375 clock-names = "pclk"; [all …]
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A D | stm32mp151.dtsi | 57 #clock-cells = <0>; 63 #clock-cells = <0>; 69 #clock-cells = <0>; 75 #clock-cells = <0>; 81 #clock-cells = <0>; 131 clock-names = "int"; 164 clock-names = "int"; 198 clock-names = "int"; 230 clock-names = "int"; 264 clock-names = "int"; [all …]
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A D | stm32mp153.dtsi | 13 clock-frequency = <650000000>; 41 clock-names = "hclk", "cclk"; 54 clock-names = "hclk", "cclk";
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A D | stm32mp15xx-dhcom-pdk2.dtsi | 18 clk_ext_audio_codec: clock-codec { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 clock-frequency = <24000000>; 222 clock-names = "pclk", "x8k", "x11k"; 229 #clock-cells = <0>; 232 clock-names = "sai_ck"; 250 clock-names = "sai_ck", "MCLK";
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A D | stm32mp157.dtsi | 16 clock-names = "bus" ,"core"; 24 clock-names = "pclk", "ref", "px_clk";
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A D | dt_driver_test.dtsi | 14 clock-names = "clk0", "clk1"; 40 #clock-cells = <1>;
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A D | stm32mp15xx-dhcor-avenger96.dtsi | 23 #clock-cells = <0>; 24 compatible = "fixed-clock"; 25 clock-frequency = <24000000>; 227 clock-names = "cec"; 242 adi,input-clock = "1x"; 294 clock-names = "pclk", "x8k", "x11k"; 298 #clock-cells = <0>; 301 clock-names = "sai_ck";
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A D | at91-sama5d27_som1.dtsi | 22 clock-frequency = <32768>; 26 clock-frequency = <24000000>;
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A D | fsl-lx2160a.dtsi | 436 #clock-cells = <0>; 518 #clock-cells = <2>; 568 clock-names = "i2c"; 580 clock-names = "i2c"; 591 clock-names = "i2c"; 602 clock-names = "i2c"; 613 clock-names = "i2c"; 625 clock-names = "i2c"; 636 clock-names = "i2c"; 647 clock-names = "i2c"; [all …]
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A D | stm32mp15xx-dhcom-som.dtsi | 453 /* clock-names = "ETH_RX_CLK/ETH_REF_CLK"; Not supported */ 456 * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, 457 * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, 458 * so that MCO2 behaves as a divider for the ETHRX clock here. 461 /* assigned-clock-parents = <&rcc PLL4_P>; Not supported */ 462 /* assigned-clock-rates = <50000000>, <100000000>; Not supported */
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A D | stm32mp15xx-dkx.dtsi | 214 clock-names = "MCLK"; 244 clock-frequency = <400000>; 424 clock-frequency = <400000>; 433 clock-names = "pclk", "i2sclk", "x8k", "x11k"; 501 clock-names = "pclk", "x8k", "x11k"; 508 #clock-cells = <0>; 511 clock-names = "sai_ck"; 529 clock-names = "sai_ck", "MCLK";
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A D | stm32mp157c-ev1.dts | 27 #clock-cells = <0>; 28 compatible = "fixed-clock"; 29 clock-frequency = <24000000>; 181 clock-names = "xclk";
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A D | stm32mp135f-dk.dts | 9 #include <dt-bindings/clock/stm32mp13-clksrc.h> 208 /* CK_MPU clock config for MP13 */
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/optee_os-3.20.0/core/arch/arm/plat-stm32mp1/ |
A D | scmi_server.c | 395 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) in plat_scmi_clock_get_name() 398 return clock->name; in plat_scmi_clock_get_name() 407 if (!clock) in plat_scmi_clock_rates_array() 432 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) in plat_scmi_clock_get_rate() 442 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) in plat_scmi_clock_get_state() 453 if (!clock) in plat_scmi_clock_set_state() 460 if (!clock->enabled) { in plat_scmi_clock_set_state() 462 clk_enable(clock->clk); in plat_scmi_clock_set_state() 463 clock->enabled = true; in plat_scmi_clock_set_state() 466 if (clock->enabled) { in plat_scmi_clock_set_state() [all …]
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/optee_os-3.20.0/core/drivers/clk/ |
A D | clk-stm32mp15.c | 750 unsigned long clock = 0; in get_clock_rate() local 759 clock = osc_frequency(OSC_HSI); in get_clock_rate() 762 clock = osc_frequency(OSC_HSE); in get_clock_rate() 773 clock = 0; in get_clock_rate() 881 clock = osc_frequency(OSC_HSI); in get_clock_rate() 885 clock = osc_frequency(OSC_CSI); in get_clock_rate() 889 clock = osc_frequency(OSC_HSE); in get_clock_rate() 895 clock = osc_frequency(OSC_HSE); in get_clock_rate() 900 clock = osc_frequency(OSC_LSI); in get_clock_rate() 903 clock = osc_frequency(OSC_LSE); in get_clock_rate() [all …]
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/optee_os-3.20.0/core/drivers/ |
A D | stm32_rng.c | 43 struct clk *clock; member 129 clk_enable(dev->clock); in gate_rng() 138 clk_disable(dev->clock); in gate_rng() 255 assert(dt_info.clock != DT_INFO_INVALID_CLOCK && in stm32_rng_init() 270 res = clk_dt_get_by_index(fdt, node, 0, &stm32_rng->clock); in stm32_rng_init() 274 assert(stm32_rng->clock); in stm32_rng_init()
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A D | stm32_iwdg.c | 84 struct clk *clock; member 154 clk_enable(iwdg->clock); in configure_timeout() 163 clk_disable(iwdg->clock); in configure_timeout() 170 clk_enable(iwdg->clock); in iwdg_start() 172 clk_disable(iwdg->clock); in iwdg_start() 179 clk_enable(iwdg->clock); in iwdg_refresh() 181 clk_disable(iwdg->clock); in iwdg_refresh() 261 res = clk_dt_get_by_name(fdt, node, "pclk", &iwdg->clock); in stm32_iwdg_parse_fdt()
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A D | stm32_i2c.c | 320 clk_enable(hi2c->clock); in save_cfg() 328 clk_disable(hi2c->clock); in save_cfg() 335 clk_enable(hi2c->clock); in restore_cfg() 345 clk_disable(hi2c->clock); in restore_cfg() 361 clk_enable(hi2c->clock); in dump_i2c() 369 clk_disable(hi2c->clock); in dump_i2c() 770 hi2c->clock = init_data->clock; in stm32_i2c_init() 776 clk_enable(hi2c->clock); in stm32_i2c_init() 1096 clk_enable(hi2c->clock); in i2c_write() 1229 clk_enable(hi2c->clock); in stm32_i2c_read_write_membyte() [all …]
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A D | stm32_tamp.c | 110 struct clk *clock; member 232 return clk_dt_get_by_index(fdt, node, 0, &tamp->clock); in stm32_tamp_parse_fdt() 251 clk_enable(tamp->clock); in stm32_tamp_probe() 287 clk_disable(tamp->clock); in stm32_tamp_probe()
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A D | stm32_uart.c | 156 res = clk_dt_get_by_index(fdt, node, 0, &pd->clock); in stm32_uart_init_from_dt_node() 162 res = clk_enable(pd->clock); in stm32_uart_init_from_dt_node()
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/optee_os-3.20.0/core/include/drivers/ |
A D | stm32_uart.h | 17 struct clk *clock; member
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A D | stm32_i2c.h | 54 struct clk *clock; member 121 struct clk *clock; member
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/optee_os-3.20.0/core/drivers/scmi-msg/ |
A D | sub.mk | 2 srcs-$(CFG_SCMI_MSG_CLOCK) += clock.c
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/optee_os-3.20.0/core/drivers/crypto/stm32/ |
A D | stm32_cryp.h | 25 struct clk *clock; member
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