| /optee_os-3.20.0/core/arch/arm/plat-imx/ |
| A D | imx_src.c | 11 uint32_t imx_get_src_gpr(int cpu) in imx_get_src_gpr() argument
16 return io_read32(va + SRC_GPR1_MX7 + cpu * 8 + 4); in imx_get_src_gpr()
18 return io_read32(va + SRC_GPR1 + cpu * 8 + 4); in imx_get_src_gpr()
21 void imx_set_src_gpr(int cpu, uint32_t val) in imx_set_src_gpr() argument
26 io_write32(va + SRC_GPR1_MX7 + cpu * 8 + 4, val); in imx_set_src_gpr()
28 io_write32(va + SRC_GPR1 + cpu * 8 + 4, val); in imx_set_src_gpr()
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| A D | imx.h | 31 uint32_t imx_get_src_gpr(int cpu);
32 void imx_set_src_gpr(int cpu, uint32_t val);
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| A D | conf.mk | 96 include core/arch/arm/cpu/cortex-a7.mk
105 include core/arch/arm/cpu/cortex-a7.mk
151 include core/arch/arm/cpu/cortex-a7.mk
155 include core/arch/arm/cpu/cortex-a7.mk
161 include core/arch/arm/cpu/cortex-a7.mk
417 include core/arch/arm/cpu/cortex-a9.mk
475 include core/arch/arm/cpu/cortex-armv8-0.mk
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| /optee_os-3.20.0/core/arch/arm/plat-imx/pm/ |
| A D | cpuidle-imx7d.c | 89 static void imx_pen_lock(uint32_t cpu) in imx_pen_lock() argument
100 if (cpu == 0) { in imx_pen_lock()
103 atomic_store_u32(&p->val, cpu); in imx_pen_lock()
107 && atomic_load_u32(&p->val) == cpu) in imx_pen_lock()
112 atomic_store_u32(&p->val, cpu); in imx_pen_lock()
121 static void imx_pen_unlock(int cpu) in imx_pen_unlock() argument
133 if (cpu == 0) in imx_pen_unlock()
161 uint32_t cpu = get_core_pos(); in imx7d_lowpower_idle() local
169 imx_pen_lock(cpu); in imx7d_lowpower_idle()
193 imx_pen_unlock(cpu); in imx7d_lowpower_idle()
[all …]
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| A D | psci.c | 123 uint32_t cpu, val; in psci_affinity_info() local
126 cpu = affinity; in psci_affinity_info()
131 wfi = io_read32(gpr5) & ARM_WFI_STAT_MASK(cpu); in psci_affinity_info()
133 if ((imx_get_src_gpr(cpu) == 0) || !wfi) in psci_affinity_info()
136 DMSG("cpu: %" PRIu32 "GPR: %" PRIx32, cpu, imx_get_src_gpr(cpu)); in psci_affinity_info()
142 while (io_read32(va + SRC_GPR1_MX7 + cpu * 8 + 4) != UINT_MAX) in psci_affinity_info()
146 val &= ~BIT32(SRC_A7RCR1_A7_CORE1_ENABLE_OFFSET + (cpu - 1)); in psci_affinity_info()
149 while (io_read32(va + SRC_GPR1 + cpu * 8 + 4) != UINT32_MAX) in psci_affinity_info()
154 val &= ~BIT32(SRC_SCR_CORE1_ENABLE_OFFSET + cpu - 1); in psci_affinity_info()
155 val |= BIT32(SRC_SCR_CORE1_RST_OFFSET + cpu - 1); in psci_affinity_info()
[all …]
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| /optee_os-3.20.0/core/arch/arm/plat-ls/ |
| A D | conf.mk | 12 include core/arch/arm/cpu/cortex-armv8-0.mk
21 include core/arch/arm/cpu/cortex-armv8-0.mk
29 include core/arch/arm/cpu/cortex-armv8-0.mk
37 include core/arch/arm/cpu/cortex-armv8-0.mk
46 include core/arch/arm/cpu/cortex-armv8-0.mk
55 include core/arch/arm/cpu/cortex-armv8-0.mk
73 include core/arch/arm/cpu/cortex-armv8-0.mk
91 include core/arch/arm/cpu/cortex-armv8-0.mk
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| /optee_os-3.20.0/core/arch/arm/plat-sunxi/ |
| A D | psci.c | 48 #define REG_CPUCFG_CPU_RST(cpu) (0x0040 + (cpu) * (0x0040)) argument
53 #define REG_PRCM_CPU_PWR_CLAMP(cpu) (0x0140 + (cpu) * (0x0004)) argument
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| A D | conf.mk | 7 include core/arch/arm/cpu/cortex-a7.mk
30 include core/arch/arm/cpu/cortex-armv8-0.mk
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| /optee_os-3.20.0/core/arch/arm/plat-ti/ |
| A D | conf.mk | 7 include core/arch/arm/cpu/cortex-a15.mk
14 include core/arch/arm/cpu/cortex-a15.mk
21 include core/arch/arm/cpu/cortex-a9.mk
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| /optee_os-3.20.0/core/arch/arm/dts/ |
| A D | fsl-lx2160a.dtsi | 27 cpu0: cpu@0 {
28 device_type = "cpu";
44 cpu1: cpu@1 {
61 cpu100: cpu@100 {
78 cpu101: cpu@101 {
95 cpu200: cpu@200 {
112 cpu201: cpu@201 {
129 cpu300: cpu@300 {
146 cpu301: cpu@301 {
163 cpu400: cpu@400 {
[all …]
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| A D | stm32mp153.dtsi | 11 cpu1: cpu@1 {
14 device_type = "cpu";
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| /optee_os-3.20.0/core/arch/arm/plat-rockchip/ |
| A D | conf.mk | 12 include ./core/arch/arm/cpu/cortex-a7.mk
30 include core/arch/arm/cpu/cortex-armv8-0.mk
48 include core/arch/arm/cpu/cortex-armv8-0.mk
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| /optee_os-3.20.0/core/arch/arm/plat-marvell/ |
| A D | conf.mk | 4 include core/arch/arm/cpu/cortex-armv8-0.mk
18 include core/arch/arm/cpu/cortex-armv8-0.mk
33 include core/arch/arm/cpu/cortex-armv8-0.mk
52 include core/arch/arm/cpu/cortex-armv8-0.mk
71 include core/arch/arm/cpu/cortex-armv8-0.mk
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| /optee_os-3.20.0/core/arch/arm/plat-vexpress/ |
| A D | conf.mk | 4 include core/arch/arm/cpu/cortex-a15.mk
7 include core/arch/arm/cpu/cortex-armv8-0.mk
11 include core/arch/arm/cpu/cortex-armv8-0.mk
24 include core/arch/arm/cpu/cortex-armv8-0.mk
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| /optee_os-3.20.0/core/arch/arm/plat-sprd/ |
| A D | conf.mk | 3 include core/arch/arm/cpu/cortex-armv8-0.mk
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| /optee_os-3.20.0/core/arch/arm/plat-amlogic/ |
| A D | conf.mk | 3 include core/arch/arm/cpu/cortex-armv8-0.mk
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| /optee_os-3.20.0/core/arch/arm/plat-aspeed/ |
| A D | conf.mk | 4 include core/arch/arm/cpu/cortex-a7.mk
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| /optee_os-3.20.0/core/arch/arm/plat-poplar/ |
| A D | conf.mk | 1 include core/arch/arm/cpu/cortex-armv8-0.mk
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| /optee_os-3.20.0/core/arch/arm/plat-synquacer/ |
| A D | conf.mk | 7 include core/arch/arm/cpu/cortex-armv8-0.mk
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| /optee_os-3.20.0/core/arch/arm/plat-zynq7k/ |
| A D | conf.mk | 3 include core/arch/arm/cpu/cortex-a9.mk
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| /optee_os-3.20.0/core/arch/arm/plat-d06/ |
| A D | conf.mk | 1 include core/arch/arm/cpu/cortex-armv8-0.mk
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| /optee_os-3.20.0/core/arch/arm/plat-d02/ |
| A D | conf.mk | 1 include core/arch/arm/cpu/cortex-armv8-0.mk
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| /optee_os-3.20.0/core/arch/arm/plat-rzn1/ |
| A D | conf.mk | 3 include core/arch/arm/cpu/cortex-a7.mk
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| /optee_os-3.20.0/core/arch/arm/plat-hisilicon/ |
| A D | conf.mk | 6 include core/arch/arm/cpu/cortex-armv8-0.mk
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| /optee_os-3.20.0/core/arch/arm/plat-rpi3/ |
| A D | conf.mk | 1 include core/arch/arm/cpu/cortex-armv8-0.mk
|