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Searched refs:div_id (Results 1 – 5 of 5) sorted by relevance

/optee_os-3.20.0/core/drivers/clk/
A Dclk-stm32-core.c252 uint32_t stm32_div_get_value(int div_id) in stm32_div_get_value() argument
255 const struct div_cfg *divider = &priv->div[div_id]; in stm32_div_get_value()
271 if (div_id >= priv->nb_div) in stm32_div_set_value()
274 divider = &priv->div[div_id]; in stm32_div_set_value()
289 const struct div_cfg *divider = &priv->div[div_id]; in stm32_div_get_rate()
290 uint32_t val = stm32_div_get_value(div_id); in stm32_div_get_rate()
304 const struct div_cfg *divider = &priv->div[div_id]; in stm32_div_set_rate()
313 return stm32_div_set_value(div_id, value); in stm32_div_set_rate()
384 return stm32_div_get_rate(cfg->div_id, parent_rate); in clk_stm32_divider_get_rate()
429 if (cfg->div_id == NO_DIV) in clk_stm32_composite_get_rate()
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A Dclk-stm32-core.h75 int div_id; member
80 int div_id; member
125 TEE_Result stm32_div_set_rate(int div_id, unsigned long rate,
128 uint32_t stm32_div_get_value(int div_id);
129 TEE_Result stm32_div_set_value(uint32_t div_id, uint32_t value);
202 .div_id = (_div_id),\
240 .div_id = (_div_id),\
A Dclk-stm32mp13.c1002 int div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT; in stm32_clk_configure_div() local
1005 return stm32_div_set_value(div_id, div_n); in stm32_clk_configure_div()
1933 .div_id = (NO_DIV),\
1963 .div_id = (_div_id),\
2003 .div_id = DIV_PLL1DIVP,
2019 .div_id = DIV_MPU,
2082 .div_id = DIV_AXI,
2094 .div_id = DIV_MLAHB,
A Dclk-stm32mp15.c729 enum stm32mp1_div_id div_id) in stm32mp1_read_pll_freq() argument
736 if (div_id >= _DIV_NB) in stm32mp1_read_pll_freq()
740 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; in stm32mp1_read_pll_freq()
/optee_os-3.20.0/core/include/dt-bindings/clock/
A Dstm32mp13-clksrc.h67 #define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
68 ((div_id) << DIV_ID_SHIFT) |\

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