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/optee_os-3.20.0/core/drivers/crypto/caam/
A Dcrypto.mk120 define cryphw-enable-drv-hw
133 $(eval $(call cryphw-enable-drv-hw, HASH))
134 $(eval $(call cryphw-enable-drv-hw, CIPHER))
140 $(eval $(call cryphw-enable-drv-hw, RSA))
141 $(eval $(call cryphw-enable-drv-hw, ECC))
142 $(eval $(call cryphw-enable-drv-hw, DH))
143 $(eval $(call cryphw-enable-drv-hw, DSA))
155 $(eval $(call cryphw-enable-drv-hw, RSA))
156 $(eval $(call cryphw-enable-drv-hw, ECC))
157 $(eval $(call cryphw-enable-drv-hw, DH))
[all …]
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_6_7/
A Dhal_clk_mx6.c12 void caam_hal_clk_enable(bool enable) in caam_hal_clk_enable() argument
24 if (enable) in caam_hal_clk_enable()
36 if (enable) in caam_hal_clk_enable()
A Dhal_clk_mx7.c12 void caam_hal_clk_enable(bool enable) in caam_hal_clk_enable() argument
16 if (enable) { in caam_hal_clk_enable()
A Dhal_clk_mx7ulp.c12 void caam_hal_clk_enable(bool enable) in caam_hal_clk_enable() argument
17 if (enable) in caam_hal_clk_enable()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_8ulp/
A Dhal_clk.c12 void caam_hal_clk_enable(bool enable) in caam_hal_clk_enable() argument
17 if (enable) in caam_hal_clk_enable()
/optee_os-3.20.0/core/arch/arm/plat-imx/pm/
A Dgpcv2.c19 void imx_gpcv2_set_core_pgc(bool enable, uint32_t offset) in imx_gpcv2_set_core_pgc() argument
23 if (enable) in imx_gpcv2_set_core_pgc()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/ls/
A Dhal_clk.c10 void caam_hal_clk_enable(bool enable __unused) in caam_hal_clk_enable()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_8m/
A Dhal_clk.c10 void caam_hal_clk_enable(bool enable __unused) in caam_hal_clk_enable()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_8q/
A Dhal_clk.c8 void caam_hal_clk_enable(bool enable __unused) in caam_hal_clk_enable()
/optee_os-3.20.0/core/drivers/crypto/caam/include/
A Dcaam_hal_clk.h17 void caam_hal_clk_enable(bool enable);
/optee_os-3.20.0/core/arch/arm/plat-stm32mp1/drivers/
A Dstm32mp1_pwr.c58 void stm32mp1_pwr_regulator_set_state(enum pwr_regulator id, bool enable) in stm32mp1_pwr_regulator_set_state() argument
65 if (enable) { in stm32mp1_pwr_regulator_set_state()
A Dstm32mp1_pwr.h31 void stm32mp1_pwr_regulator_set_state(enum pwr_regulator id, bool enable);
/optee_os-3.20.0/core/drivers/clk/
A Dclk-stm32-core.c65 static void stm32_gate_endisable(uint16_t gate_id, bool enable) in stm32_gate_endisable() argument
71 if (enable) { in stm32_gate_endisable()
127 static TEE_Result stm32_gate_ready_endisable(uint16_t gate_id, bool enable, in stm32_gate_ready_endisable() argument
130 stm32_gate_endisable(gate_id, enable); in stm32_gate_ready_endisable()
133 return stm32_gate_wait_ready(gate_id + 1, enable); in stm32_gate_ready_endisable()
354 .enable = clk_stm32_gate_enable,
374 .enable = clk_stm32_gate_ready_enable,
467 .enable = clk_stm32_composite_gate_enable,
/optee_os-3.20.0/core/
A Dcrypto.mk68 $(eval $(call cryp-enable-all-depends,CFG_WITH_SOFTWARE_PRNG, AES ECB SHA256))
117 cryp-enable-all-depends = $(call cfg-enable-all-depends,$(strip $(1)),$(foreach v,$(2),CFG_CRYPTO_$…
118 $(eval $(call cryp-enable-all-depends,CFG_REE_FS, AES ECB CTR HMAC SHA256 GCM))
119 $(eval $(call cryp-enable-all-depends,CFG_RPMB_FS, AES ECB CTR HMAC SHA256 GCM))
/optee_os-3.20.0/core/drivers/
A Dsp805_wdt.c46 static void sp805_config(struct wdt_chip *chip, bool enable) in sp805_config() argument
56 if (enable) in sp805_config()
A Dstpmic1.c876 int stpmic1_lp_reg_on_off(const char *name, uint8_t enable) in stpmic1_lp_reg_on_off() argument
883 return stpmic1_register_update(regul->low_power_reg, enable, in stpmic1_lp_reg_on_off()
887 int stpmic1_lp_on_off_unpg(struct stpmic1_lp_cfg *cfg, int enable) in stpmic1_lp_on_off_unpg() argument
889 assert(cfg->lp_reg && (enable == 0 || enable == 1)); in stpmic1_lp_on_off_unpg()
891 return stpmic1_register_update(cfg->lp_reg, enable, in stpmic1_lp_on_off_unpg()
/optee_os-3.20.0/core/arch/arm/plat-imx/
A Dimx.h56 void imx_gpcv2_set_core_pgc(bool enable, uint32_t offset);
/optee_os-3.20.0/core/arch/arm/dts/
A Dstm32mp157c-ev1.dts297 /* spare dmas for other usage (un-delete to enable pwm capture) */
375 st,enable-fs-rftime-tuning;
376 st,enable-hs-rftime-reduction;
386 st,enable-fs-rftime-tuning;
387 st,enable-hs-rftime-reduction;
/optee_os-3.20.0/core/drivers/clk/sam/
A Dat91_main.c83 .enable = pmc_main_rc_osc_enable,
165 .enable = pmc_main_osc_enable,
281 .enable = clk_sam9x5_main_enable,
A Dat91_master.c73 .enable = clk_master_enable,
105 .enable = clk_master_enable,
A Dat91_audio_pll.c278 .enable = clk_audio_pll_frac_enable,
285 .enable = clk_audio_pll_pad_enable,
292 .enable = clk_audio_pll_pmc_enable,
A Dat91_system.c59 .enable = clk_system_enable,
/optee_os-3.20.0/mk/
A Dcheckconf.mk152 cfg-enable-all-depends = \
161 $(call cfg-enable-all-depends,$(1),$(filter-out $(firstword $(2)),$(2))), \
/optee_os-3.20.0/core/include/drivers/
A Dstpmic1.h180 int stpmic1_lp_reg_on_off(const char *name, uint8_t enable);
237 int stpmic1_lp_on_off_unpg(struct stpmic1_lp_cfg *cfg, int enable);
/optee_os-3.20.0/core/drivers/scmi-msg/
A Dclock.c220 bool enable = false; in scmi_clock_config_set() local
236 enable = in_args->attributes & SCMI_CLOCK_CONFIG_SET_ENABLE_MASK; in scmi_clock_config_set()
238 status = plat_scmi_clock_set_state(msg->channel_id, clock_id, enable); in scmi_clock_config_set()

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