Home
last modified time | relevance | path

Searched refs:io_caam_read32 (Results 1 – 9 of 9) sorted by relevance

/optee_os-3.20.0/core/drivers/crypto/caam/hal/common/
A Dhal_ctrl.c19 uint32_t val = io_caam_read32(baseaddr + CCBVID); in caam_hal_ctrl_era()
30 val = io_caam_read32(baseaddr + CHANUM_MS); in caam_hal_ctrl_jrnum()
33 val = io_caam_read32(baseaddr + JR_VERSION); in caam_hal_ctrl_jrnum()
46 val = io_caam_read32(baseaddr + CHANUM_LS); in caam_hal_ctrl_hash_limit()
50 val = io_caam_read32(baseaddr + CHAVID_LS); in caam_hal_ctrl_hash_limit()
59 val = io_caam_read32(baseaddr + MDHA_VERSION); in caam_hal_ctrl_hash_limit()
87 val = io_caam_read32(baseaddr + CHANUM_LS); in caam_hal_ctrl_pknum()
90 val = io_caam_read32(baseaddr + PKHA_VERSION); in caam_hal_ctrl_pknum()
107 val = io_caam_read32(baseaddr + SCFGR); in caam_hal_ctrl_inc_priblob()
120 val = io_caam_read32(baseaddr + SCFGR); in caam_hal_ctrl_inc_priblob()
[all …]
A Dhal_jr.c48 reg_val = io_caam_read32(baseaddr + JRX_JRINTR); in caam_hal_jr_reset()
62 reg_val = io_caam_read32(baseaddr + JRX_JRCR); in caam_hal_jr_reset()
121 return io_caam_read32(baseaddr + JRX_IRSAR); in caam_hal_jr_read_nbslot_available()
131 return io_caam_read32(baseaddr + JRX_ORSFR); in caam_hal_jr_get_nbjob_done()
160 val = io_caam_read32(baseaddr + JRX_JRINTR); in caam_hal_jr_check_ack_itr()
183 val = io_caam_read32(baseaddr + JRX_IRSR); in caam_hal_jr_halt()
191 val = io_caam_read32(baseaddr + JRX_JRINTR); in caam_hal_jr_halt()
213 val = io_caam_read32(baseaddr + JRX_IRSR); in caam_hal_jr_flush()
221 val = io_caam_read32(baseaddr + JRX_JRINTR); in caam_hal_jr_flush()
240 return io_caam_read32(baseaddr + JRX_IRRIR) >> 2; in caam_hal_jr_input_index()
[all …]
A Dhal_rng.c23 vid = io_caam_read32(baseaddr + CHAVID_LS); in caam_hal_rng_instantiated()
28 vid = io_caam_read32(baseaddr + RNG_VERSION); in caam_hal_rng_instantiated()
50 reg = io_caam_read32(baseaddr + CTPR_MS); in caam_hal_rng_get_nb_sh()
57 return io_caam_read32(baseaddr + RNG_STA) & (RNG_STA_IF1 | RNG_STA_IF0); in caam_hal_rng_get_sh_status()
62 return io_caam_read32(baseaddr + RNG_STA) & RNG_STA_SKVN; in caam_hal_rng_key_loaded()
90 val = io_caam_read32(baseaddr + TRNG_SDCTL); in caam_hal_rng_kick()
129 val = io_caam_read32(baseaddr + TRNG_MCTL); in caam_hal_rng_kick()
/optee_os-3.20.0/core/drivers/crypto/caam/include/
A Dcaam_io.h17 #define io_caam_read32(a) TEE_U32_FROM_BIG_ENDIAN(io_read32(a)) macro
25 #define io_caam_read32(a) io_read32(a) macro
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_8m/
A Dhal_jr.c33 val = io_caam_read32(ctrl_base + JRxDID_MS(jr_idx)); in caam_hal_jr_setowner()
62 val = io_caam_read32(ctrl_base + JRxDID_LS(jr_idx)); in caam_hal_jr_setowner()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_6_7/
A Dhal_jr.c33 val = io_caam_read32(ctrl_base + JRxMIDR_MS(jr_idx)); in caam_hal_jr_setowner()
66 val = io_caam_read32(ctrl_base + JRxMIDR_LS(jr_idx)); in caam_hal_jr_setowner()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_8ulp/
A Dhal_jr.c34 val = io_caam_read32(ctrl_base + JRxDID_MS(jr_idx)); in caam_hal_jr_setowner()
63 val = io_caam_read32(ctrl_base + JRxDID_LS(jr_idx)); in caam_hal_jr_setowner()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/ls/
A Dhal_jr.c22 val = io_caam_read32(ctrl_base + JRxMIDR_MS(jr_idx)); in caam_hal_jr_setowner()
/optee_os-3.20.0/core/drivers/crypto/caam/
A Dcaam_pwr.c71 io_caam_read32(elem->baseaddr + in do_save_regs()

Completed in 7 milliseconds