| /optee_os-3.20.0/core/drivers/ |
| A D | bcm_sotp.c | 96 io_clrbits32((bcm_sotp_base + SOTP_PROG_CONTROL), in bcm_iproc_sotp_mem_read()
123 io_clrbits32((bcm_sotp_base + SOTP_CTRL_0), SOTP_CTRL_0__START); in bcm_iproc_sotp_mem_read()
138 io_clrbits32((bcm_sotp_base + SOTP_PROG_CONTROL), in bcm_iproc_sotp_mem_read()
190 io_clrbits32(bcm_sotp_base + SOTP_PROG_CONTROL, in bcm_iproc_sotp_mem_write()
194 io_clrbits32(bcm_sotp_base + SOTP_PROG_CONTROL, in bcm_iproc_sotp_mem_write()
227 io_clrbits32(bcm_sotp_base + SOTP_CTRL_0, SOTP_CTRL_0__START); in bcm_iproc_sotp_mem_write()
267 io_clrbits32(bcm_sotp_base + SOTP_PROG_CONTROL, in bcm_iproc_sotp_mem_write()
271 io_clrbits32(bcm_sotp_base + SOTP_CTRL_0, SOTP_CTRL_0__START); in bcm_iproc_sotp_mem_write()
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| A D | ls_gpio.c | 72 io_clrbits32(gpio_data_addr, PIN_SHIFT(gpio_pin)); in gpio_set_value()
121 io_clrbits32(gpio_dir_addr, PIN_SHIFT(gpio_pin)); in gpio_set_direction()
170 io_clrbits32(gpio_ier_addr, PIN_SHIFT(gpio_pin)); in gpio_set_interrupt()
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| A D | imx_snvs.c | 100 io_clrbits32(base + SNVS_LPMKCR, SNVS_LPMKCR_MKCR_MKS_SEL); in set_mks_otpmk()
101 io_clrbits32(base + SNVS_HPLR, SNVS_HPLR_MKS_SL); in set_mks_otpmk()
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| A D | atmel_piobu.c | 104 io_clrbits32(piobu_addr, SECUMOD_PIOBU_SOD); in gpio_set_value()
149 io_clrbits32(piobu_addr, SECUMOD_PIOBU_OUTPUT); in gpio_set_direction()
192 io_clrbits32(niepr_addr, SECUMOD_PIN_VAL(gpio_pin)); in gpio_set_interrupt()
262 io_clrbits32(piobu_addr, SECUMOD_PIOBU_OUTPUT); in secumod_cfg_input_pio()
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| A D | zynqmp_csudma.c | 103 io_clrbits32(dma + CSUDMA_CTRL_OFFSET, CSUDMA_CTRL_ENDIAN_MASK); in zynqmp_csudma_unprepare()
105 io_clrbits32(dma + CSUDMA_CTRL_OFFSET, CSUDMA_CTRL_ENDIAN_MASK); in zynqmp_csudma_unprepare()
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| A D | bcm_hwrng.c | 40 io_clrbits32(bcm_hwrng_base + in bcm_hwrng_reset()
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| A D | bcm_gpio.c | 74 io_clrbits32(gc->base + offset, BIT(shift)); in iproc_clr_bit()
171 io_clrbits32(regaddr, BIT(shift)); in iproc_gpio_set_secure()
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| A D | stm32_i2c.c | 337 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); in restore_cfg()
668 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); in i2c_config_analog_filter()
671 io_clrbits32(base + I2C_CR1, I2C_CR1_ANFOFF); in i2c_config_analog_filter()
782 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); in stm32_i2c_init()
919 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); in i2c_ack_failed()
1176 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); in i2c_write()
1279 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); in stm32_i2c_read_write_membyte()
1394 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); in i2c_read()
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| A D | imx_rngb.c | 98 io_clrbits32(rng->base.va + RNG_CR, in irq_unmask()
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| A D | ls_dspi.c | 354 io_clrbits32(data->base + DSPI_MCR, DSPI_MCR_HALT); in ls_dspi_start()
409 io_clrbits32(dspi_data->base + DSPI_MCR, DSPI_MCR_PCSIS(cs)); in dspi_set_cs_active_state()
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| A D | imx_ocotp.c | 100 io_clrbits32(g_base_addr + OCOTP_CTRL, OCOTP_CTRL_ERROR); in imx_ocotp_read()
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| A D | stm32_tamp.c | 199 io_clrbits32(base + _TAMP_SMCR, _TAMP_SMCR_DPROT); in stm32_tamp_set_secure()
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| /optee_os-3.20.0/core/arch/arm/plat-stm32mp1/drivers/ |
| A D | stm32mp1_syscfg.c | 66 io_clrbits32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); in stm32mp_syscfg_enable_io_compensation()
79 io_clrbits32(syscfg_base + SYSCFG_CMPCR, in stm32mp_syscfg_disable_io_compensation()
89 io_clrbits32(syscfg_base + SYSCFG_CMPENSETR, SYSCFG_CMPENSETR_MPU_EN); in stm32mp_syscfg_disable_io_compensation()
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| A D | stm32mp1_pwr.c | 78 io_clrbits32(cr3, enable_mask); in stm32mp1_pwr_regulator_set_state()
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| /optee_os-3.20.0/core/arch/arm/plat-sunxi/ |
| A D | psci.c | 101 io_clrbits32(cpucfg + REG_CPUCFG_GEN_CTRL, BIT32(core_idx)); in psci_cpu_on()
105 io_clrbits32(cpucfg + REG_CPUCFG_DBG_CTRL1, BIT32(core_idx)); in psci_cpu_on()
118 io_clrbits32(base + REG_PRCM_CPU_PWROFF, BIT32(core_idx)); in psci_cpu_on()
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| A D | main.c | 177 io_clrbits32(base + SMC_MASTER_BYPASS, SMC_MASTER_BYPASS_EN_MASK); in smc_init()
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| /optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_8ulp/ |
| A D | hal_clk.c | 20 io_clrbits32(pcc3_base + PCC_CAAM, PCC_ENABLE_CLOCK); in caam_hal_clk_enable()
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| /optee_os-3.20.0/core/drivers/clk/sam/ |
| A D | at91_audio_pll.c | 79 io_clrbits32(frac->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_enable()
128 io_clrbits32(frac->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_disable()
131 io_clrbits32(frac->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_disable()
139 io_clrbits32(apad_ck->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_pad_disable()
147 io_clrbits32(apmc_ck->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_pmc_disable()
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| A D | at91_utmi.c | 92 io_clrbits32(utmi->pmc_base + AT91_CKGR_UCKR, AT91_PMC_UPLLEN); in clk_utmi_disable()
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| /optee_os-3.20.0/core/arch/arm/plat-sam/ |
| A D | sam_sfr.c | 38 io_clrbits32(sam_sfr_base() + AT91_SFR_OHCIICR, in atmel_sfr_set_usb_suspend()
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| /optee_os-3.20.0/core/arch/arm/plat-hisilicon/ |
| A D | psci.c | 88 io_clrbits32(crg + REG_CPU_SUSSYS_RESET, RELEASE_CORE_MASK); in psci_cpu_on()
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| /optee_os-3.20.0/core/drivers/imx/mu/ |
| A D | imx_mu_8q.c | 57 io_clrbits32(base + MU_ACR_OFFSET, in imx_mu_plat_init()
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| /optee_os-3.20.0/core/arch/arm/plat-rzn1/ |
| A D | main.c | 93 io_clrbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_MIREQ_A); in rzn1_cm3_start()
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| /optee_os-3.20.0/core/drivers/rstctrl/ |
| A D | stm32_rstctrl.c | 68 io_clrbits32(rcc_base + RCC_MP_GCR, RCC_MP_GCR_BOOT_MCU); in reset_assert()
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| /optee_os-3.20.0/core/include/ |
| A D | io.h | 233 static inline void io_clrbits32(vaddr_t addr, uint32_t clear_mask) in io_clrbits32() function
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