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Searched refs:io_read32 (Results 1 – 25 of 114) sorted by relevance

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/optee_os-3.20.0/core/drivers/
A Dls_sec_mon.c124 data->hplr = io_read32((vaddr_t)&sec_mon_regs->hplr); in ls_sec_mon_read()
125 data->hpcomr = io_read32((vaddr_t)&sec_mon_regs->hpcomr); in ls_sec_mon_read()
126 data->hpsicr = io_read32((vaddr_t)&sec_mon_regs->hpsicr); in ls_sec_mon_read()
127 data->hpsvcr = io_read32((vaddr_t)&sec_mon_regs->hpsvcr); in ls_sec_mon_read()
128 data->hpsr = io_read32((vaddr_t)&sec_mon_regs->hpsr); in ls_sec_mon_read()
129 data->hpsvsr = io_read32((vaddr_t)&sec_mon_regs->hpsvsr); in ls_sec_mon_read()
131 data->hphacr = io_read32((vaddr_t)&sec_mon_regs->hphacr); in ls_sec_mon_read()
132 data->lplr = io_read32((vaddr_t)&sec_mon_regs->lplr); in ls_sec_mon_read()
133 data->lpcr = io_read32((vaddr_t)&sec_mon_regs->lpcr); in ls_sec_mon_read()
134 data->lpmkcr = io_read32((vaddr_t)&sec_mon_regs->lpmkcr); in ls_sec_mon_read()
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A Dls_sfp.c186 if (io_read32(sfp_ingr_va) & SFP_INGR_ERROR_MASK) { in ls_sfp_program_fuses()
212 data->ingr = io_read32((vaddr_t)&sfp_regs->ingr); in ls_sfp_read()
214 data->sfpcr = io_read32((vaddr_t)&sfp_regs->sfpcr); in ls_sfp_read()
216 data->ospr0 = io_read32((vaddr_t)&sfp_regs->ospr0); in ls_sfp_read()
217 data->ospr1 = io_read32((vaddr_t)&sfp_regs->ospr1); in ls_sfp_read()
218 data->dcvr0 = io_read32((vaddr_t)&sfp_regs->dcvr0); in ls_sfp_read()
219 data->dcvr1 = io_read32((vaddr_t)&sfp_regs->dcvr1); in ls_sfp_read()
220 data->drvr0 = io_read32((vaddr_t)&sfp_regs->drvr0); in ls_sfp_read()
221 data->drvr1 = io_read32((vaddr_t)&sfp_regs->drvr1); in ls_sfp_read()
341 ospr1 = io_read32((vaddr_t)&sfp_regs->ospr1); in ls_sfp_set_debug_level()
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A Dimx_snvs.c67 hp_mks = io_read32(base + SNVS_HPCOMR); in is_otpmk_selected()
74 uint32_t lp_mks = io_read32(base + SNVS_LPMKCR); in is_otpmk_selected()
90 return io_read32(base + SNVS_HPLR) & SNVS_HPLR_MKS_SL || in is_mks_locked()
91 io_read32(base + SNVS_LPLR) & SNVS_LPLR_MKS_HL; in is_mks_locked()
111 uint32_t status = io_read32(base + SNVS_HPSR); in is_otpmk_valid()
122 val = (io_read32(base + SNVS_HPSR) & SNVS_HPSR_SYS_SECURITY_CFG) >> in snvs_get_security_cfg()
149 val = io_read32(snvs + SNVS_HPSR); in snvs_get_ssm_mode()
A Dtzc380.c57 return io_read32(base + BUILD_CONFIG_OFF); in tzc_read_build_config()
67 return io_read32(base + ACTION_OFF); in tzc_read_action()
84 return io_read32(base + REGION_ATTRIBUTES_OFF(region)); in tzc_read_region_attributes()
146 io_read32(base + FAIL_ADDRESS_LOW_OFF)); in tzc_fail_dump()
148 io_read32(base + FAIL_ADDRESS_HIGH_OFF)); in tzc_fail_dump()
150 EMSG("Fail Id 0x%" PRIx32, io_read32(base + FAIL_ID)); in tzc_fail_dump()
305 check = io_read32(tzc.base + LOCKDOWN_RANGE_OFF); in tzc_regions_lockdown()
311 check = io_read32(tzc.base + LOCKDOWN_SELECT_OFF); in tzc_regions_lockdown()
338 io_read32(tzc.base + SECURITY_INV_EN_OFF)); in tzc_dump_state()
355 io_read32(tzc.base + LOCKDOWN_SELECT_OFF)); in tzc_dump_state()
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A Dlpc_uart.c33 status = io_read32(LPC_IRQ_ST_REG_OFFSET + addr); in lpc_byte_read()
38 status = io_read32(LPC_IRQ_ST_REG_OFFSET + addr); in lpc_byte_read()
43 if (io_read32(LPC_OP_STATUS_REG_OFFSET + addr) & LPC_IRQ_ST_ON) in lpc_byte_read()
44 *data = io_read32(LPC_RDATA_REG_OFFSET + addr); in lpc_byte_read()
59 status = io_read32(LPC_IRQ_ST_REG_OFFSET + addr); in lpc_byte_write()
64 status = io_read32(LPC_IRQ_ST_REG_OFFSET + addr); in lpc_byte_write()
A Ddra7_rng.c79 while (!(io_read32(rng + RNG_STATUS) & RNG_READY)) { in dra7_rng_read64()
81 if (io_read32(rng + RNG_STATUS) & SHUTDOWN_OFLO) { in dra7_rng_read64()
82 uint32_t alarm = io_read32(rng + RNG_ALARMSTOP); in dra7_rng_read64()
83 uint32_t tune = io_read32(rng + RNG_FRODETUNE); in dra7_rng_read64()
99 *low_word = io_read32(rng + RNG_OUTPUT_L); in dra7_rng_read64()
100 *high_word = io_read32(rng + RNG_OUTPUT_H); in dra7_rng_read64()
141 while (io_read32(rng + RNG_SOFT_RESET_REG) & RNG_SOFT_RESET) in dra7_rng_init()
A Damlogic_uart.c37 while (!(io_read32(base + AML_UART_STATUS) & AML_UART_TX_EMPTY)) in amlogic_uart_flush()
45 if (io_read32(base + AML_UART_STATUS) & AML_UART_RX_EMPTY) in amlogic_uart_getchar()
48 return io_read32(base + AML_UART_RFIFO) & 0xff; in amlogic_uart_getchar()
55 while (io_read32(base + AML_UART_STATUS) & AML_UART_TX_FULL) in amlogic_uart_putc()
A Datmel_uart.c65 while (!(io_read32(base + ATMEL_UART_SR) & ATMEL_SR_TXEMPTY)) in atmel_uart_flush()
73 while (io_read32(base + ATMEL_UART_SR) & ATMEL_SR_RXRDY) in atmel_uart_getchar()
76 return io_read32(base + ATMEL_UART_RHR); in atmel_uart_getchar()
83 while (!(io_read32(base + ATMEL_UART_SR) & ATMEL_SR_TXRDY)) in atmel_uart_putc()
A Dimx_uart.c99 while (!(io_read32(base + UTS) & UTS_TXEMPTY)) in imx_uart_flush()
100 if (!(io_read32(base + UCR1) & UCR1_UARTEN)) in imx_uart_flush()
108 while (io_read32(base + UTS) & UTS_RXEMPTY) in imx_uart_getchar()
111 return (io_read32(base + URXD) & URXD_RX_DATA); in imx_uart_getchar()
119 while (io_read32(base + UTS) & UTS_TXFULL) in imx_uart_putc()
120 if (!(io_read32(base + UCR1) & UCR1_UARTEN)) in imx_uart_putc()
A Dtzc400.c84 return io_read32(base + BUILD_CONFIG_OFF); in tzc_read_build_config()
89 return io_read32(base + GATE_KEEPER_OFF); in tzc_read_gate_keeper()
104 return io_read32(base + REGION_BASE_LOW_OFF + REGION_NUM_OFF(region)); in tzc_read_region_base_low()
126 return io_read32(base + REGION_TOP_LOW_OFF + REGION_NUM_OFF(region)); in tzc_read_region_top_low()
137 return io_read32(base + REGION_TOP_HIGH_OFF + REGION_NUM_OFF(region)); in tzc_read_region_top_high()
387 return io_read32(tzc.base + FAIL_CONTROL(filter)) & in write_not_read()
393 return io_read32(tzc.base + FAIL_CONTROL(filter)) & in nonsecure_not_secure()
399 return io_read32(tzc.base + FAIL_CONTROL(filter)) & in priv_not_unpriv()
406 uint32_t status = io_read32(tzc.base + INT_STATUS); in dump_fail_filter()
423 io_read32(tzc.base + FAIL_ADDRESS_LOW(filter))); in dump_fail_filter()
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A Dxiphera_trng.c44 status = io_read32(xiphera_trng_base + STATUS_REG); in xiphera_trng_random_available()
53 value = io_read32(xiphera_trng_base + RAND_REG); in xiphera_trng_read32()
127 status = io_read32(xiphera_trng_base + STATUS_REG); in xiphera_trng_probe()
135 status = io_read32(xiphera_trng_base + STATUS_REG); in xiphera_trng_probe()
155 status = io_read32(xiphera_trng_base + STATUS_REG); in xiphera_trng_probe()
A Dcdns_uart.c71 while (!(io_read32(base + CDNS_UART_CHANNEL_STATUS) & in cdns_uart_flush()
80 return !(io_read32(base + CDNS_UART_CHANNEL_STATUS) & in cdns_uart_have_rx_data()
90 return io_read32(base + CDNS_UART_FIFO) & 0xff; in cdns_uart_getchar()
98 while (io_read32(base + CDNS_UART_CHANNEL_STATUS) & in cdns_uart_putc()
A Dmvebu_uart.c76 while (!(io_read32(base + UART_STATUS_REG) & UARTLSR_TXFIFOEMPTY)) in mvebu_uart_flush()
84 return (io_read32(base + UART_STATUS_REG) & UART_RX_READY); in mvebu_uart_have_rx_data()
93 return io_read32(base + UART_RX_REG) & 0xff; in mvebu_uart_getchar()
103 tmp = io_read32(base + UART_STATUS_REG); in mvebu_uart_putc()
A Dhi16xx_uart.c73 while (!(io_read32(base + UART_USR) & UART_USR_TFE_BIT)) in hi16xx_uart_flush()
82 while (!(io_read32(base + UART_USR) & UART_USR_TFE_BIT)) in hi16xx_uart_putc()
93 return (io_read32(base + UART_USR) & UART_USR_RFNE_BIT); in hi16xx_uart_have_rx_data()
102 return io_read32(base + UART_RBR) & 0xFF; in hi16xx_uart_getchar()
A Dsprd_uart.c56 while (io_read32(base + UART_STS1) & STS1_TXF_CNT_MASK) in sprd_uart_flush()
64 return !!(io_read32(base + UART_STS1) & STS1_RXF_CNT_MASK); in sprd_uart_have_rx_data()
82 return io_read32(base + UART_RXD) & 0xff; in sprd_uart_getchar()
/optee_os-3.20.0/core/arch/arm/plat-imx/pm/
A Dgpcv2.c21 uint32_t val = io_read32(gpc_base() + offset) & (~GPC_PGC_PCG_MASK); in imx_gpcv2_set_core_pgc()
31 uint32_t val = io_read32(gpc_base() + GPC_CPU_PGC_SW_PDN_REQ); in imx_gpcv2_set_core1_pdn_by_software()
39 while ((io_read32(gpc_base() + GPC_CPU_PGC_SW_PDN_REQ) & in imx_gpcv2_set_core1_pdn_by_software()
48 uint32_t val = io_read32(gpc_base() + GPC_CPU_PGC_SW_PUP_REQ); in imx_gpcv2_set_core1_pup_by_software()
56 while ((io_read32(gpc_base() + GPC_CPU_PGC_SW_PUP_REQ) & in imx_gpcv2_set_core1_pup_by_software()
A Dpsci.c78 val = io_read32(va + SRC_A7RCR1); in psci_cpu_on()
87 val = io_read32(va + SRC_SCR); in psci_cpu_on()
131 wfi = io_read32(gpr5) & ARM_WFI_STAT_MASK(cpu); in psci_affinity_info()
142 while (io_read32(va + SRC_GPR1_MX7 + cpu * 8 + 4) != UINT_MAX) in psci_affinity_info()
145 val = io_read32(va + SRC_A7RCR1); in psci_affinity_info()
149 while (io_read32(va + SRC_GPR1 + cpu * 8 + 4) != UINT32_MAX) in psci_affinity_info()
153 val = io_read32(va + SRC_SCR); in psci_affinity_info()
/optee_os-3.20.0/core/arch/arm/plat-k3/drivers/
A Dsa2ul_rng.c71 while (!(io_read32(rng + RNG_STATUS) & RNG_READY)) { in sa2ul_rng_read128()
73 if (io_read32(rng + RNG_STATUS) & SHUTDOWN_OFLO) { in sa2ul_rng_read128()
74 uint32_t alarm = io_read32(rng + RNG_ALARMSTOP); in sa2ul_rng_read128()
75 uint32_t tune = io_read32(rng + RNG_FRODETUNE); in sa2ul_rng_read128()
91 *word0 = io_read32(rng + RNG_OUTPUT_0); in sa2ul_rng_read128()
92 *word1 = io_read32(rng + RNG_OUTPUT_1); in sa2ul_rng_read128()
93 *word2 = io_read32(rng + RNG_OUTPUT_2); in sa2ul_rng_read128()
94 *word3 = io_read32(rng + RNG_OUTPUT_3); in sa2ul_rng_read128()
/optee_os-3.20.0/core/drivers/clk/sam/
A Dat91_pmc.c192 pmc_cache.scsr = io_read32(pmc_base + AT91_PMC_SCSR); in pmc_suspend()
193 pmc_cache.pcsr0 = io_read32(pmc_base + AT91_PMC_PCSR); in pmc_suspend()
194 pmc_cache.uckr = io_read32(pmc_base + AT91_CKGR_UCKR); in pmc_suspend()
195 pmc_cache.mor = io_read32(pmc_base + AT91_CKGR_MOR); in pmc_suspend()
196 pmc_cache.mcfr = io_read32(pmc_base + AT91_CKGR_MCFR); in pmc_suspend()
198 pmc_cache.mckr = io_read32(pmc_base + AT91_PMC_MCKR); in pmc_suspend()
199 pmc_cache.usb = io_read32(pmc_base + AT91_PMC_USB); in pmc_suspend()
200 pmc_cache.imr = io_read32(pmc_base + AT91_PMC_IMR); in pmc_suspend()
219 status = io_read32(pmc_base + AT91_PMC_SR); in pmc_ready()
232 tmp = io_read32(pmc_base + AT91_PMC_MCKR); in pmc_resume()
[all …]
A Dat91_main.c39 uint32_t status = io_read32(osc->base + AT91_PMC_SR); in pmc_main_rc_osc_ready()
47 uint32_t mor = io_read32(osc->base + AT91_CKGR_MOR); in pmc_main_rc_osc_enable()
65 uint32_t mor = io_read32(osc->base + AT91_CKGR_MOR); in pmc_main_rc_osc_disable()
123 uint32_t status = io_read32(pmc->base + AT91_PMC_SR); in pmc_main_osc_ready()
131 uint32_t mor = io_read32(pmc->base + AT91_CKGR_MOR); in pmc_main_osc_enable()
152 uint32_t mor = io_read32(pmc->base + AT91_CKGR_MOR); in pmc_main_osc_disable()
198 while (!(io_read32(base + AT91_CKGR_MCFR) & AT91_PMC_MAINRDY)) in clk_main_probe_frequency()
213 mcfr = io_read32(base + AT91_CKGR_MCFR); in clk_main_get_rate()
222 uint32_t status = io_read32(base + AT91_PMC_SR); in clk_sam9x5_main_ready()
253 tmp = io_read32(pmc->base + AT91_CKGR_MOR); in clk_sam9x5_main_set_parent()
[all …]
/optee_os-3.20.0/core/arch/arm/plat-stm32mp1/drivers/
A Dstm32mp1_syscfg.c59 while (!(io_read32(syscfg_base + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY)) in stm32mp_syscfg_enable_io_compensation()
68 DMSG("SYSCFG.cmpcr = %#"PRIx32, io_read32(syscfg_base + SYSCFG_CMPCR)); in stm32mp_syscfg_enable_io_compensation()
76 value = io_read32(syscfg_base + SYSCFG_CMPCR) >> in stm32mp_syscfg_disable_io_compensation()
82 value = io_read32(syscfg_base + SYSCFG_CMPCR) | in stm32mp_syscfg_disable_io_compensation()
87 DMSG("SYSCFG.cmpcr = %#"PRIx32, io_read32(syscfg_base + SYSCFG_CMPCR)); in stm32mp_syscfg_disable_io_compensation()
/optee_os-3.20.0/core/arch/arm/plat-sunxi/
A Dmain.c109 DMSG("SMTA_DECPORT0=%x", io_read32(v + REG_TZPC_SMTA_DECPORT0_STA_REG)); in tzpc_init()
110 DMSG("SMTA_DECPORT1=%x", io_read32(v + REG_TZPC_SMTA_DECPORT1_STA_REG)); in tzpc_init()
111 DMSG("SMTA_DECPORT2=%x", io_read32(v + REG_TZPC_SMTA_DECPORT2_STA_REG)); in tzpc_init()
118 DMSG("SMTA_DECPORT0=%x", io_read32(v + REG_TZPC_SMTA_DECPORT0_STA_REG)); in tzpc_init()
119 DMSG("SMTA_DECPORT1=%x", io_read32(v + REG_TZPC_SMTA_DECPORT1_STA_REG)); in tzpc_init()
120 DMSG("SMTA_DECPORT2=%x", io_read32(v + REG_TZPC_SMTA_DECPORT2_STA_REG)); in tzpc_init()
/optee_os-3.20.0/core/arch/arm/plat-rockchip/
A Dpsci_rk322x.c105 while (!(io_read32(va_base + CRU_PLL_CON1(pll)) & PLL_LOCK) && in pll_wait_lock()
111 if (!(io_read32(va_base + CRU_PLL_CON1(pll)) & PLL_LOCK)) { in pll_wait_lock()
125 dram_d.cru_clksel0 = io_read32(va_base + CRU_CLKSEL_CON(0)); in plls_power_down()
126 dram_d.cru_clksel1 = io_read32(va_base + CRU_CLKSEL_CON(1)); in plls_power_down()
127 dram_d.cru_clksel10 = io_read32(va_base + CRU_CLKSEL_CON(10)); in plls_power_down()
128 dram_d.cru_clksel21 = io_read32(va_base + CRU_CLKSEL_CON(21)); in plls_power_down()
129 dram_d.cru_mode_con = io_read32(va_base + CRU_MODE_CON); in plls_power_down()
209 while (!(io_read32(va_base + GRF_CPU_STATUS1) & wfei_mask) && in wait_core_wfe_i()
215 return io_read32(va_base + GRF_CPU_STATUS1) & wfei_mask; in wait_core_wfe_i()
223 val = io_read32(va_base + CRU_SOFTRST_CON(0)); in core_held_in_reset()
[all …]
/optee_os-3.20.0/core/arch/arm/plat-versal/
A Dmain.c88 if (io_read32(plm_rtca + VERSAL_AHWROT_REG) == VERSAL_AHWROT_SECURED) in platform_banner()
91 if (io_read32(plm_rtca + VERSAL_SHWROT_REG) == VERSAL_SHWROT_SECURED) in platform_banner()
108 if (io_read32(plm_rtca + VERSAL_AHWROT_REG) == VERSAL_AHWROT_SECURED) in plat_rpmb_key_is_ready()
111 if (io_read32(plm_rtca + VERSAL_SHWROT_REG) == VERSAL_SHWROT_SECURED) in plat_rpmb_key_is_ready()
/optee_os-3.20.0/core/arch/arm/plat-bcm/
A Dbcm_elog.c19 offset = io_read32(base + BCM_ELOG_OFF_OFFSET); in bcm_elog_putchar()
20 len = io_read32(base + BCM_ELOG_LEN_OFFSET); in bcm_elog_putchar()
52 val = io_read32(base + BCM_ELOG_SIG_OFFSET); in bcm_elog_init()

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