Home
last modified time | relevance | path

Searched refs:io_setbits32 (Results 1 – 25 of 41) sorted by relevance

12

/optee_os-3.20.0/core/drivers/
A Dbcm_sotp.c88 io_setbits32((bcm_sotp_base + SOTP_PROG_CONTROL), in bcm_iproc_sotp_mem_read()
99 io_setbits32((bcm_sotp_base + SOTP_PROG_CONTROL), in bcm_iproc_sotp_mem_read()
110 io_setbits32((bcm_sotp_base + SOTP_CTRL_0), SOTP_CTRL_0__START); in bcm_iproc_sotp_mem_read()
137 io_setbits32((bcm_sotp_base + SOTP_STATUS_1), SOTP_STATUS_1__CMD_DONE); in bcm_iproc_sotp_mem_read()
182 io_setbits32(bcm_sotp_base + SOTP_PROG_CONTROL, in bcm_iproc_sotp_mem_write()
187 io_setbits32(bcm_sotp_base + SOTP_PROG_CONTROL, in bcm_iproc_sotp_mem_write()
211 io_setbits32(bcm_sotp_base + SOTP_CTRL_0, SOTP_CTRL_0__START); in bcm_iproc_sotp_mem_write()
223 io_setbits32(bcm_sotp_base + SOTP_STATUS_1, in bcm_iproc_sotp_mem_write()
253 io_setbits32(bcm_sotp_base + SOTP_CTRL_0, SOTP_CTRL_0__START); in bcm_iproc_sotp_mem_write()
264 io_setbits32(bcm_sotp_base + SOTP_STATUS_1, SOTP_STATUS_1__CMD_DONE); in bcm_iproc_sotp_mem_write()
A Datmel_trng.c77 io_setbits32(trng_base + TRNG_CTRL, ctrl_val); in atmel_trng_reset()
79 io_setbits32(trng_base + TRNG_IER, 1); in atmel_trng_reset()
81 io_setbits32(trng_base + TRNG_CTRL, ctrl_val | 1); in atmel_trng_reset()
A Dls_gpio.c69 io_setbits32(gpio_data_addr, PIN_SHIFT(gpio_pin)); in gpio_set_value()
119 io_setbits32(gpio_dir_addr, PIN_SHIFT(gpio_pin)); in gpio_set_direction()
168 io_setbits32(gpio_ier_addr, PIN_SHIFT(gpio_pin)); in gpio_set_interrupt()
233 io_setbits32(gpio_data->gpio_base + GPIOIBE, UINT32_MAX); in ls_gpio_init()
A Datmel_piobu.c102 io_setbits32(piobu_addr, SECUMOD_PIOBU_SOD); in gpio_set_value()
147 io_setbits32(piobu_addr, SECUMOD_PIOBU_OUTPUT); in gpio_set_direction()
190 io_setbits32(niepr_addr, SECUMOD_PIN_VAL(gpio_pin)); in gpio_set_interrupt()
277 io_setbits32(secumod_base + SECUMOD_NMPR, SECUMOD_PIN_VAL(gpio_pin)); in secumod_cfg_input_pio()
281 io_setbits32(secumod_base + SECUMOD_WKPR, in secumod_cfg_input_pio()
A Dimx_rngb.c90 io_setbits32(rng->base.va + RNG_CR, in irq_clear()
92 io_setbits32(rng->base.va + RNG_CMD, in irq_clear()
110 io_setbits32(rng->base.va + RNG_CR, RNG_CR_AR); in rng_seed()
A Dimx_snvs.c99 io_setbits32(base + SNVS_HPCOMR, SNVS_HPCOMR_MKS_EN); in set_mks_otpmk()
102 io_setbits32(base + SNVS_LPLR, SNVS_LPLR_MKS_HL); in set_mks_otpmk()
A Dimx_ocotp.c39 io_setbits32(va + CCM_CCGR2, BM_CCM_CCGR2_OCOTP_CTRL); in ocotp_clock_enable()
46 io_setbits32(va + CCM_CCGRx_SET(CCM_CLOCK_DOMAIN_OCOTP), in ocotp_clock_enable()
54 io_setbits32(va + CCM_CCGRx_SET(CCM_CCRG_OCOTP), in ocotp_clock_enable()
A Dzynqmp_csudma.c91 io_setbits32(dma + CSUDMA_CTRL_OFFSET, CSUDMA_CTRL_ENDIAN_MASK); in zynqmp_csudma_prepare()
93 io_setbits32(dma + CSUDMA_CTRL_OFFSET, CSUDMA_CTRL_ENDIAN_MASK); in zynqmp_csudma_prepare()
A Dbcm_hwrng.c38 io_setbits32(bcm_hwrng_base + in bcm_hwrng_reset()
A Dstm32_i2c.c343 io_setbits32(base + I2C_CR1, cfg->cr1 & I2C_CR1_PE); in restore_cfg()
675 io_setbits32(base + I2C_CR1, I2C_CR1_ANFOFF); in i2c_config_analog_filter()
678 io_setbits32(base + I2C_CR1, I2C_CR1_PE); in i2c_config_analog_filter()
802 io_setbits32(base + I2C_CR2, I2C_CR2_ADD10); in stm32_i2c_init()
808 io_setbits32(base + I2C_CR2, I2C_CR2_AUTOEND | I2C_CR2_NACK); in stm32_i2c_init()
828 io_setbits32(base + I2C_CR1, I2C_CR1_PE); in stm32_i2c_init()
860 io_setbits32(base + I2C_ISR, I2C_ISR_TXE); in i2c_flush_txdr()
1502 io_setbits32(base + I2C_CR2, I2C_CR2_STOP); in stm32_i2c_is_device_ready()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/common/
A Dhal_jr.c41 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_reset()
142 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_disable_itr()
143 io_setbits32(baseaddr + JRX_JRINTR, JRX_JRINTR_JRI); in caam_hal_jr_disable_itr()
164 io_setbits32(baseaddr + JRX_JRINTR, JRX_JRINTR_JRI); in caam_hal_jr_check_ack_itr()
177 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_halt()
207 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_flush()
A Dhal_rng.c79 io_setbits32(baseaddr + TRNG_MCTL, TRNG_MCTL_PRGM | TRNG_MCTL_ACC); in caam_hal_rng_kick()
146 io_setbits32(baseaddr + TRNG_MCTL, TRNG_MCTL_ERR); in caam_hal_rng_kick()
/optee_os-3.20.0/core/arch/arm/plat-rzn1/
A Dpsci.c78 io_setbits32(core_mmu_get_va(SYSCTRL_REG_RSTEN, MEM_AREA_IO_SEC, in psci_system_reset()
83 io_setbits32(core_mmu_get_va(SYSCTRL_REG_RSTCTRL, MEM_AREA_IO_SEC, in psci_system_reset()
A Dmain.c105 io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_CLKEN_A); in rzn1_cm3_start()
106 io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_RSTN_A); in rzn1_cm3_start()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_8m/
A Dhal_ctrl.c15 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_8ulp/
A Dhal_ctrl.c16 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
A Dhal_clk.c18 io_setbits32(pcc3_base + PCC_CAAM, PCC_ENABLE_CLOCK); in caam_hal_clk_enable()
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_6_7/
A Dhal_ctrl.c29 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
/optee_os-3.20.0/core/arch/arm/plat-sunxi/
A Dpsci.c127 io_setbits32(cpucfg + REG_CPUCFG_DBG_CTRL1, BIT32(core_idx)); in psci_cpu_on()
154 io_setbits32(base + REG_PRCM_CPU_PWROFF, BIT32(core_id)); in psci_cpu_off()
/optee_os-3.20.0/core/arch/arm/plat-sam/
A Dsam_sfr.c35 io_setbits32(sam_sfr_base() + AT91_SFR_OHCIICR, in atmel_sfr_set_usb_suspend()
/optee_os-3.20.0/core/arch/arm/plat-rockchip/
A Dplatform_px30.c48 io_setbits32(fw_base + FIREWALL_DDR_FW_DDR_CON_REG, BIT(rgn)); in platform_secure_ddr_region()
/optee_os-3.20.0/core/arch/arm/plat-stm32mp1/drivers/
A Dstm32mp1_pwr.c69 io_setbits32(cr3, enable_mask); in stm32mp1_pwr_regulator_set_state()
A Dstm32mp1_syscfg.c55 io_setbits32(syscfg_base + SYSCFG_CMPENSETR, SYSCFG_CMPENSETR_MPU_EN); in stm32mp_syscfg_enable_io_compensation()
/optee_os-3.20.0/core/arch/arm/plat-imx/drivers/
A Dimx_csu.c150 io_setbits32(csu_base + CSU_SA, csu_config->sa->lock_value); in csu_init()
/optee_os-3.20.0/core/arch/arm/plat-k3/drivers/
A Dsa2ul.c136 io_setbits32(sa2ul + SA2UL_EEC, SA2UL_EEC_TRNG); in sa2ul_init()

Completed in 33 milliseconds

12