Searched refs:mux (Results 1 – 8 of 8) sorted by relevance
| /optee_os-3.20.0/core/drivers/clk/sam/ |
| A D | at91_i2s_mux.c | 23 struct clk_i2s_mux *mux = clk->priv; in clk_i2s_mux_get_parent() local
24 uint32_t val = io_read32(mux->sfr_base + AT91_SFR_I2SCLKSEL); in clk_i2s_mux_get_parent()
26 return (val & BIT(mux->bus_id)) >> mux->bus_id; in clk_i2s_mux_get_parent()
31 struct clk_i2s_mux *mux = clk->priv; in clk_i2s_mux_set_parent() local
33 io_clrsetbits32(mux->sfr_base + AT91_SFR_I2SCLKSEL, in clk_i2s_mux_set_parent()
34 BIT(mux->bus_id), index << mux->bus_id); in clk_i2s_mux_set_parent()
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| /optee_os-3.20.0/core/arch/arm/dts/ |
| A D | fsl-lx2160a-qds.dts | 33 mdio-mux-1 {
34 compatible = "mdio-mux-multiplexer";
35 mux-controls = <&mux 0>;
101 mdio-mux-2 {
102 compatible = "mdio-mux-multiplexer";
103 mux-controls = <&mux 1>;
230 mux: mux-controller { label
231 compatible = "reg-mux";
232 #mux-control-cells = <1>;
233 mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
[all …]
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| A D | fsl-lx2160a-rdb.dts | 82 i2c-mux@77 {
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| A D | stm32mp151.dtsi | 367 clock-names = "mux";
1196 clock-names = "mux";
1225 clock-names = "mux";
1247 clock-names = "mux";
1263 clock-names = "mux";
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| A D | stm32mp15xx-dhcom-som.dtsi | 164 st,fmc2-ebi-cs-mux-enable;
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| /optee_os-3.20.0/core/drivers/ |
| A D | imx_i2c.c | 449 struct imx_i2c_mux *mux = &i2c_mux; in imx_i2c_init() local
460 io_write32(mux->base.va + mux->i2c[bid].scl_mux, I2C_MUX_VAL(bid)); in imx_i2c_init()
461 io_write32(mux->base.va + mux->i2c[bid].scl_cfg, I2C_CFG_VAL(bid)); in imx_i2c_init()
462 if (mux->i2c[bid].scl_inp) in imx_i2c_init()
463 io_write32(mux->base.va + mux->i2c[bid].scl_inp, in imx_i2c_init()
466 io_write32(mux->base.va + mux->i2c[bid].sda_mux, I2C_MUX_VAL(bid)); in imx_i2c_init()
467 io_write32(mux->base.va + mux->i2c[bid].sda_cfg, I2C_CFG_VAL(bid)); in imx_i2c_init()
468 if (mux->i2c[bid].sda_inp) in imx_i2c_init()
469 io_write32(mux->base.va + mux->i2c[bid].sda_inp, in imx_i2c_init()
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| /optee_os-3.20.0/core/drivers/clk/ |
| A D | clk-stm32-core.c | 43 const struct mux_cfg *mux = &priv->muxes[mux_id]; in stm32_mux_get_parent() local
44 uint32_t mask = MASK_WIDTH_SHIFT(mux->width, mux->shift); in stm32_mux_get_parent()
46 return (io_read32(priv->base + mux->offset) & mask) >> mux->shift; in stm32_mux_get_parent()
52 const struct mux_cfg *mux = &priv->muxes[mux_id]; in stm32_mux_set_parent() local
53 uint32_t mask = MASK_WIDTH_SHIFT(mux->width, mux->shift); in stm32_mux_set_parent()
54 uintptr_t address = priv->base + mux->offset; in stm32_mux_set_parent()
56 io_clrsetbits32(address, mask, (sel << mux->shift) & mask); in stm32_mux_set_parent()
58 if (mux->ready != MUX_NO_RDY) in stm32_mux_set_parent()
59 return stm32_gate_wait_ready((uint16_t)mux->ready, true); in stm32_mux_set_parent()
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| A D | clk-stm32mp13.c | 941 int mux = -1; in stm32_clk_configure_clk() local
948 mux = MUX_MCO1; in stm32_clk_configure_clk()
953 mux = MUX_MCO2; in stm32_clk_configure_clk()
964 if (stm32_mux_set_parent(mux, sel)) in stm32_clk_configure_clk()
978 int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT; in stm32_clk_configure_mux() local
981 if (mux == MUX_RTC) { in stm32_clk_configure_mux()
992 if (stm32_mux_set_parent(mux, sel)) in stm32_clk_configure_mux()
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