Searched refs:pll (Results 1 – 6 of 6) sorted by relevance
| /optee_os-3.20.0/core/arch/arm/plat-rockchip/ |
| A D | cru.h | 39 #define CRU_PLL_CON0(pll) ((pll) * 0x0c + 0x0) argument
40 #define CRU_PLL_CON1(pll) ((pll) * 0x0c + 0x4) argument
41 #define CRU_PLL_CON2(pll) ((pll) * 0x0c + 0x8) argument
47 #define PLL_MODE_BIT(pll) ((pll) * 4) argument
48 #define PLL_MODE_MSK(pll) BIT(PLL_MODE_BIT(pll)) argument
49 #define PLL_SLOW_MODE(pll) BITS_WITH_WMASK(0, 1, PLL_MODE_BIT(pll)) argument
50 #define PLL_NORM_MODE(pll) BITS_WITH_WMASK(1, 1, PLL_MODE_BIT(pll)) argument
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| A D | psci_rk322x.c | 85 static void pll_power_down(uint32_t pll) in pll_power_down() argument
89 io_write32(va_base + CRU_MODE_CON, PLL_SLOW_MODE(pll)); in pll_power_down()
90 io_write32(va_base + CRU_PLL_CON1(pll), PLL_POWER_DOWN); in pll_power_down()
93 static void pll_power_up(uint32_t pll) in pll_power_up() argument
97 io_write32(va_base + CRU_PLL_CON1(pll), PLL_POWER_UP); in pll_power_up()
100 static void pll_wait_lock(uint32_t pll) in pll_wait_lock() argument
105 while (!(io_read32(va_base + CRU_PLL_CON1(pll)) & PLL_LOCK) && in pll_wait_lock()
111 if (!(io_read32(va_base + CRU_PLL_CON1(pll)) & PLL_LOCK)) { in pll_wait_lock()
112 EMSG("PLL can't lock, index = %" PRIu32, pll); in pll_wait_lock()
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| /optee_os-3.20.0/core/drivers/clk/sam/ |
| A D | at91_pll.c | 74 (div == pll->div && mul == pll->mul)) in clk_pll_enable()
90 while (!clk_pll_ready(pll->base, pll->id)) in clk_pll_enable()
101 io_clrsetbits32(pll->base + PLL_REG(pll->id), mask, ~mask); in clk_pll_disable()
109 if (!pll->div || !pll->mul) in clk_pll_get_rate()
112 return (parent_rate / pll->div) * (pll->mul + 1); in clk_pll_get_rate()
242 pll->div = div; in clk_pll_set_rate()
243 pll->mul = mul; in clk_pll_set_rate()
276 pll = calloc(1, sizeof(*pll)); in at91_clk_register_pll()
277 if (!pll) { in at91_clk_register_pll()
282 pll->id = id; in at91_clk_register_pll()
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| /optee_os-3.20.0/core/arch/arm/dts/ |
| A D | stm32mp135f-dk.dts | 152 pll1: st,pll@0 {
153 compatible = "st,stm32mp1-pll";
156 st,pll = < &pll1_cfg1 >;
170 pll2: st,pll@1 {
174 st,pll = < &pll2_cfg1 >;
183 pll3: st,pll@2 {
187 st,pll = < &pll3_cfg1 >;
196 pll4: st,pll@3 {
199 st,pll = < &pll4_cfg1 >;
214 st,pll = < &pll1_cfg2 >;
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| /optee_os-3.20.0/core/drivers/clk/ |
| A D | clk-stm32mp13.c | 92 struct stm32_pll_dt_cfg *pll; member
1131 const struct stm32_clk_pll *pll, in clk_stm32_is_pll_config_on_the_fly() argument
1186 const struct stm32_clk_pll *pll, in clk_stm32_pll_config_vco() argument
1211 const struct stm32_clk_pll *pll, in clk_stm32_pll_config_csg() argument
1239 const struct stm32_clk_pll *pll, in clk_stm32_pll_config_out() argument
1255 return &pdata->pll[pll_idx]; in clk_stm32_pll_get_pdata()
1326 if (stm32_gate_rdy_disable(pll->gate_id)) in clk_stm32_pll_init()
1344 if (stm32_gate_rdy_enable(pll->gate_id)) in clk_stm32_pll_init()
1535 struct stm32_pll_dt_cfg *pll) in clk_stm32_parse_pll_fdt() argument
1575 struct stm32_pll_dt_cfg *pll = pdata->pll + i; in stm32_clk_parse_fdt_all_pll() local
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| A D | clk-stm32mp15.c | 679 return osc_frequency(pll->refclk[src]); in stm32mp1_pll_get_fref()
697 cfgr1 = io_read32(stm32_rcc_base() + pll->pllxcfgr1); in stm32mp1_pll_get_fvco()
698 fracr = io_read32(stm32_rcc_base() + pll->pllxfracr); in stm32mp1_pll_get_fvco()
703 refclk = stm32mp1_pll_get_fref(pll); in stm32mp1_pll_get_fvco()
731 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_read_pll_freq() local
739 cfgr2 = io_read32(stm32_rcc_base() + pll->pllxcfgr2); in stm32mp1_read_pll_freq()
742 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); in stm32mp1_read_pll_freq()
1091 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in get_parent_id_parent() local
1093 p_sel = io_read32(stm32_rcc_base() + pll->rckxselr) & in get_parent_id_parent()
1096 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) in get_parent_id_parent()
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