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/optee_os-3.20.0/core/arch/arm/plat-imx/
A Da9_plat_init.S83 read_diag r0
84 orr r0, r0, #1 << 22
85 write_diag r0
95 mov r0, #SCR_AW
96 write_scr r0
121 write_sctlr r0
128 write_actlr r0
131 write_nsacr r0
133 read_pcr r0
134 orr r0, r0, #0x1
[all …]
A Da7_plat_init.S43 mov_imm r0, 0x00006040
44 write_actlr r0
46 mov_imm r0, 0x00040C00
47 write_nsacr r0
54 and r0, r0, #MPIDR_CPU_MASK
/optee_os-3.20.0/core/arch/arm/kernel/
A Dentry_a32.S91 lsl r0, r0, #2
122 add r0, r0, #4
148 bic r0, r0, #SCTLR_I
152 orr r0, r0, #SCTLR_A
154 bic r0, r0, #SCTLR_A
232 orr r0, r0, r2
281 add r0, r0, #1
407 add r0, r0, r2
461 add r0, r0, r2
616 sub r0, r0, r1
[all …]
A Dthread_a32.S118 ldm r0, {r0-r12}
237 ldm r0, {r0-r7}
324 ldm r0, {r0-r12}
396 bic r0, r0, #1
401 bic r0, r0, #TTBCR_PD1
410 ldr r0, [r0]
819 ldr r0, [r0]
844 orr r0, r0, #TTBCR_PD1
849 orr r0, r0, #BIT(0)
928 bic r0, r0, r3
[all …]
A Dmisc_a32.S15 read_mpidr r0
22 mov r3, r0
31 tst r0, #MPIDR_MT_MASK
32 lsleq r3, r0, #MPIDR_AFFINITY_BITS
42 add r0, r0, r1, LSL #(CFG_CORE_CLUSTER_SHIFT)
52 add r0, r0, r1, LSL #(CFG_CORE_THREAD_SHIFT)
63 mov r1, r0
69 orr r0, r1 /* set expected mode */
79 msr cpsr, r0 /* set the new mode */
100 lsrs r0, r0, #2
[all …]
A Dtz_ssvce_pl310_a32.S32 subs r0, r0, #1
74 ldr r1, [r0, #PL310_SYNC]
79 str r1, [r0, #PL310_SYNC]
82 ldr r1, [r0, #PL310_SYNC]
102 ldr r1, [r0, #PL310_SYNC]
107 str r1, [r0, #PL310_SYNC]
110 ldr r1, [r0, #PL310_SYNC]
163 sub r0, r0, #(PL310_BASE - SCU_BASE)
167 add r0, r0, #(PL310_BASE - SCU_BASE)
170 str r1, [r0, r3]
[all …]
A Dthread_optee_smc_a32.S50 mov r1, r0
60 push {r0-r7}
61 mov r0, sp
87 mov r1, r0
98 mov r1, r0
109 mov r1, r0
120 mov r1, r0
131 mov r1, r0
142 mov r1, r0
182 mov sp, r0
[all …]
A Dthread_spmc_a32.S17 mov_imm r0, FFA_MSG_WAIT /* FID */
38 push {r0-r7}
39 mov r0, sp
45 pop {r0-r7}
56 mov r5, r0 /* Save return value */
61 mov sp, r0
76 push {r0, lr}
77 UNWIND( .save {r0, lr})
95 ldr r0, =FFA_MSG_SEND_DIRECT_RESP_32
127 mla r1, r1, r0, r2
[all …]
A Dcache_helpers_a32.S35 add r1, r0, r1
37 bic r0, r0, r3
39 write_\reg r0
40 add r0, r0, r2
41 cmp r0, r1
134 orr r0, r0, r7, LSL r10 // factor in the set number
154 write_dcisw r0
158 write_dccsw r0
254 bic r0, r0, r3
257 add r0, r0, r2
[all …]
/optee_os-3.20.0/core/arch/arm/plat-stm/
A Dtz_a9init.S31 str r1, [r0, #PL310_CTRL]
36 read_actlr r0
37 orrne r0, r0, #(1 << 3) /* enable ACTLR[FLZW] */
38 write_actlr r0
53 mov_imm r0, SCR_AW
54 write_scr r0
57 write_sctlr r0
60 write_actlr r0
63 write_nsacr r0
65 mov_imm r0, CPU_PCR_INIT
[all …]
/optee_os-3.20.0/core/arch/arm/plat-sunxi/
A Dplat_init.S36 read_nsacr r0
37 orr r0, r0, #NSACR_CP10
38 orr r0, r0, #NSACR_CP11
39 orr r0, r0, #NSACR_NS_SMP
40 write_nsacr r0
43 read_actlr r0
44 orr r0, r0, #ACTLR_SMP
45 write_actlr r0
/optee_os-3.20.0/core/arch/arm/sm/
A Dpsci-helper.S12 read_actlr r0
13 bic r0, r0, #ACTLR_SMP
14 write_actlr r0
20 read_actlr r0
21 orr r0, r0, #ACTLR_SMP
22 write_actlr r0
31 mov r0, #DCACHE_OP_CLEAN_INV
35 read_sctlr r0
36 bic r0, r0, #SCTLR_C
37 write_sctlr r0
[all …]
A Dsm_a32.S43 stm r0!, {r2}
48 stm r0!, {r2}
77 ldm r0!, {r2}
82 ldm r0!, {r2}
99 push {r0-r7}
127 cmp r0, r9
158 read_scr r0
184 mov r0, sp
195 pop {r0-r7}
340 orr r0, r0, #SCR_NS /* Set NS bit in SCR */
[all …]
A Dpm_a32.S30 push {r0, r1}
33 add r0, sp, #8
37 pop {r0, pc}
42 mov r0, #(-1)
99 adr r0, _core_pos
100 ldr r1, [r0]
101 add r0, r0, r1
102 blx r0
117 mla r0, r0, r1, r4
119 ldr r0, [r0, #THREAD_CORE_LOCAL_SM_PM_CTX_PHYS]
[all …]
/optee_os-3.20.0/core/lib/libtomcrypt/src/ciphers/
A Dserpent.c79 r3 ^= r0; \
83 r1 ^= r0; \
84 r0 |= r3; \
85 r0 ^= r4; \
94 r3 |= r0; \
102 r1 |= r0; \
107 r0 ^= r4; \
108 r2 ^= r0; \
122 r0 = ~r0; \
267 r0 = ~r0; \
[all …]
/optee_os-3.20.0/core/arch/arm/plat-zynq7k/
A Dplat_init.S68 mov r0, #SCR_AW
69 write_scr r0 /* write Secure Configuration Register */
91 mov_imm r0, 0x00004000
92 write_sctlr r0
94 mov_imm r0, 0x00000041
95 write_actlr r0
97 mov_imm r0, 0x00020C00
98 write_nsacr r0
100 mov_imm r0, 0x00000001
101 write_pcr r0
/optee_os-3.20.0/core/arch/arm/plat-hisilicon/
A Dhi3519av100_plat_init.S40 mrrc p15, 1, r0, r1, c15
41 orr r0, r0, #CPUECTLR_A53_SMPEN
50 read_scr r0
51 orr r0, r0, #SCR_NS /* Set NS bit in SCR */
52 write_scr r0
60 bic r0, r0, #SCR_NS /* Clr NS bit in SCR */
61 write_scr r0
76 cmp r0, #0
78 ldr r0, =CCI_BASE
79 ldr r1, [r0]
[all …]
/optee_os-3.20.0/core/arch/arm/plat-rzn1/
A Da7_plat_init.S35 mov r0, #SCR_AW
36 write_scr r0
38 mov_imm r0, 0x00000000
39 write_sctlr r0
51 mov_imm r0, 0x00006040
52 write_actlr r0
60 mov_imm r0, 0x00000C00
61 write_nsacr r0
/optee_os-3.20.0/core/arch/arm/plat-ls/
A Dplat_init.S62 mov r0, #SCR_AW
63 write_scr r0 /* write Secure Configuration Register */
77 mov_imm r0, 0x00000000
78 write_sctlr r0
80 mov_imm r0, 0x00000040
81 write_actlr r0
83 mov_imm r0, 0x00000C00
84 write_nsacr r0
/optee_os-3.20.0/lib/libutils/ext/arch/arm/
A Dmcount_a32.S31 stmdb sp!, {r0-r3, lr}
33 ldr r0, [sp, #20] /* lr of instrumented func */
34 mcount_adj_pc r0, r0
40 ldr r0, [sp, #16]
41 mcount_adj_pc r0, r0
46 ldmia sp!, {r0-r3, ip, lr}
53 stmdb sp!, {r0-r3}
57 mov lr, r0
60 ldmia sp!, {r0-r3}
/optee_os-3.20.0/core/arch/arm/plat-vexpress/
A Djuno_core_pos_a32.S13 and r1, r0, #MPIDR_CPU_MASK
14 and r0, r0, #MPIDR_CLUSTER_MASK
15 eor r0, r0, #(1 << MPIDR_CLUSTER_SHIFT)
16 add r0, r1, r0, LSR #6
/optee_os-3.20.0/core/lib/libtomcrypt/src/stream/sosemanuk/
A Dsosemanuk.c73 r1 ^= r0; r0 |= r3; \
83 r0 = ~r0; r2 = ~r2; \
84 r4 = r0; r0 &= r1; \
85 r2 ^= r0; r0 |= r3; \
91 r1 ^= r0; r0 &= r2; \
96 r4 = r0; r0 &= r2; \
101 r3 ^= r0; r0 &= r1; \
107 r4 = r0; r0 |= r3; \
125 r2 ^= r0; r0 &= r1; \
127 r4 ^= r0; r0 |= r3; \
[all …]
/optee_os-3.20.0/core/arch/arm/plat-ti/
A Da9_plat_init.S54 cmp r0, #CFG_TEE_CORE_NB_CORE
59 add r0, r0, #1
62 mul r1, r0, r1
63 ldr r0, =stack_tmp
66 sub r0, r0, r2
68 add sp, r1, r0
75 ldr r0, =suspend_regs
82 mov r0, r5
87 mov r0, #TEESMC_OPTEED_RETURN_ENTRY_DONE
/optee_os-3.20.0/lib/libutils/isoc/arch/arm/
A Darm32_aeabi_ldivmod_a32.S16 push {r0-r3}
17 UNWIND( .save {r0-r3})
18 mov r0, sp
20 pop {r0-r3}
31 push {r0-r3}
32 UNWIND( .save {r0-r3})
33 mov r0, sp
35 pop {r0-r3}
/optee_os-3.20.0/core/arch/arm/plat-stm32mp1/
A Dreset.S17 ldr r0, =SCR_SIF
18 write_scr r0
20 read_nsacr r0
22 and r0, r0, r1
23 write_nsacr r0

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