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Searched refs:reg (Results 1 – 25 of 84) sorted by relevance

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/optee_os-3.20.0/core/arch/arm/mm/
A Dtee_pager.c451 assert(va >= reg->base && va < (reg->base + reg->size)); in region_va2tblidx()
488 assert(va >= reg->base && va < (reg->base + reg->size)); in pmem_assign_fobj_page()
610 reg = calloc(1, sizeof(*reg)); in alloc_region()
758 reg = TAILQ_NEXT(reg, link); in pager_add_um_region()
879 if (va == reg->base || va == reg->base + reg->size) in tee_pager_split_um_region()
881 if (va > reg->base && va < reg->base + reg->size) { in tee_pager_split_um_region()
972 if (reg->base + reg->size < va) in tee_pager_merge_um_region()
1084 reg = TAILQ_NEXT(reg, fobj_link); in same_context()
1171 reg = TAILQ_NEXT(reg, link); in tee_pager_set_um_region_attr()
1203 assert(va >= reg->base && va < (reg->base + reg->size)); in pmem_find()
[all …]
/optee_os-3.20.0/core/drivers/crypto/caam/hal/imx_6_7/
A Dhal_clk_mx6.c16 uint32_t reg = 0; in caam_hal_clk_enable() local
19 reg = io_read32(ccm_base + CCM_CCGR0); in caam_hal_clk_enable()
25 reg |= mask; in caam_hal_clk_enable()
27 reg &= ~mask; in caam_hal_clk_enable()
29 io_write32(ccm_base + CCM_CCGR0, reg); in caam_hal_clk_enable()
33 reg = io_read32(ccm_base + CCM_CCGR6); in caam_hal_clk_enable()
37 reg |= mask; in caam_hal_clk_enable()
39 reg &= ~mask; in caam_hal_clk_enable()
41 io_write32(ccm_base + CCM_CCGR6, reg); in caam_hal_clk_enable()
/optee_os-3.20.0/core/arch/arm/include/
A Darm32_macros_cortex_a9.S31 .macro write_pcr reg
32 mcr p15, 0, \reg, c15, c0, 0
35 .macro read_pcr reg
36 mrc p15, 0, \reg, c15, c0, 0
39 .macro write_diag reg
40 mcr p15, 0, \reg, c15, c0, 1
43 .macro read_diag reg
44 mrc p15, 0, \reg, c15, c0, 1
A Darm64_macros.S30 base_offs, reg
123 .macro adr_l reg, sym
124 adrp \reg, \sym
125 add \reg, \reg, :lo12:\sym
136 .macro read_apiakeylo reg
137 mrs \reg, S3_0_c2_c1_0
140 .macro read_apiakeyhi reg
141 mrs \reg, S3_0_c2_c1_1
144 .macro write_apiakeylo reg
145 msr S3_0_c2_c1_0, \reg
[all …]
A Darm32_macros.S11 .macro mov_imm reg, val
13 movw \reg, #(\val)
15 movw \reg, #((\val) & 0xffff)
16 movt \reg, #((\val) >> 16)
A Darm64.h366 #define DEFINE_U32_REG_READ_FUNC(reg) \ argument
367 DEFINE_REG_READ_FUNC_(reg, uint32_t, reg)
369 #define DEFINE_U32_REG_WRITE_FUNC(reg) \ argument
370 DEFINE_REG_WRITE_FUNC_(reg, uint32_t, reg)
373 DEFINE_U32_REG_READ_FUNC(reg) \
374 DEFINE_U32_REG_WRITE_FUNC(reg)
376 #define DEFINE_U64_REG_READ_FUNC(reg) \ argument
377 DEFINE_REG_READ_FUNC_(reg, uint64_t, reg)
380 DEFINE_REG_WRITE_FUNC_(reg, uint64_t, reg)
383 DEFINE_U64_REG_READ_FUNC(reg) \
[all …]
/optee_os-3.20.0/core/arch/arm/dts/
A Dfsl-lx2160a-qds.dts41 reg = <0x00>;
47 reg = <0x8>;
53 reg = <0x18>;
59 reg = <0x19>;
65 reg = <0x1a>;
71 reg = <0x1b>;
77 reg = <0x1c>;
83 reg = <0x1d>;
177 reg = <0>;
189 reg = <0>;
[all …]
A Dstm32mp131.dtsi23 reg = <0>;
199 reg = <0x0 0x2>;
202 reg = <0x4 0x2>;
205 reg = <0x10 0x4>;
208 reg = <0x24 0x4>;
211 reg = <0x34 0xc>;
214 reg = <0x48 0x4>;
217 reg = <0x5c 0x2>;
220 reg = <0x5e 0x2>;
223 reg = <0x60 0x20>;
[all …]
A Dstm32mp151.dtsi22 reg = <0>;
148 reg = <1>;
182 reg = <2>;
214 reg = <3>;
248 reg = <4>;
271 reg = <5>;
289 reg = <6>;
311 reg = <11>;
379 reg = <0>;
585 reg = <1>;
[all …]
A Dfsl-lx2160a.dtsi31 reg = <0x0>;
48 reg = <0x1>;
65 reg = <0x100>;
82 reg = <0x101>;
99 reg = <0x200>;
116 reg = <0x201>;
133 reg = <0x300>;
150 reg = <0x301>;
167 reg = <0x400>;
184 reg = <0x401>;
[all …]
A Dsama5d2.dtsi33 reg = <0>;
47 reg = <0x740000 0x1000>;
63 reg = <0x73c000 0x1000>;
98 reg = <0x00200000 0x20000>;
235 reg = <0>;
536 reg = <0x200 0x200>;
555 reg = <0x400 0x200>;
576 reg = <0x600 0x200>;
606 reg = <0x200 0x200>;
625 reg = <0x400 0x200>;
[all …]
A Dfsl-lx2160a-rdb.dts62 reg = <0>;
73 reg = <1>;
84 reg = <0x77>;
91 reg = <0x2>;
95 reg = <0x40>;
103 reg = <0x3>;
107 reg = <0x4c>;
113 reg = <0x4d>;
125 reg = <0x51>;
A Dat91-sama5d27_som1.dtsi44 reg = <0>;
52 reg = <0x00000000 0x00040000>;
57 reg = <0x00040000 0x000c0000>;
62 reg = <0x00100000 0x00040000>;
67 reg = <0x00140000 0x00040000>;
72 reg = <0x00180000 0x00080000>;
77 reg = <0x00200000 0x00600000>;
88 reg = <0x7>;
104 reg = <0x50>;
A Dstm32mp157c-dk2.dts34 reg = <0xec 0x4>;
45 reg = <0>;
52 reg = <1>;
61 reg = <0>;
77 reg = <0x38>;
92 reg = <1>;
/optee_os-3.20.0/lib/libunw/
A Dunwind_arm32.c184 if (!copy_in(reg, (void *)*vsp, sizeof(*reg))) in pop_vsp()
186 (*vsp) += sizeof(*reg); in pop_vsp()
210 unsigned int reg; in unwind_exec_insn() local
225 for (reg = 4; mask && reg < 16; mask >>= 1, reg++) { in unwind_exec_insn()
230 state->update_mask |= 1 << reg; in unwind_exec_insn()
233 if (reg == SP) in unwind_exec_insn()
246 unsigned int count, reg; in unwind_exec_insn() local
255 for (reg = 4; reg <= 4 + count; reg++) { in unwind_exec_insn()
259 state->update_mask |= 1 << reg; in unwind_exec_insn()
275 unsigned int reg; in unwind_exec_insn() local
[all …]
/optee_os-3.20.0/core/drivers/crypto/caam/
A Dcaam_pwr.c59 const struct reglist *reg = NULL; in do_save_regs() local
65 reg = elem->regs; in do_save_regs()
68 for (regidx = 0; regidx < reg->nbregs; in do_save_regs()
72 reg->offset + in do_save_regs()
74 elem->val[validx] &= ~reg->mask_clr; in do_save_regs()
77 elem->baseaddr + reg->offset + in do_save_regs()
89 const struct reglist *reg = NULL; in do_restore_regs() local
95 reg = elem->regs; in do_restore_regs()
98 for (regidx = 0; regidx < reg->nbregs; in do_restore_regs()
101 elem->baseaddr + reg->offset + in do_restore_regs()
[all …]
/optee_os-3.20.0/core/arch/arm/plat-rzn1/
A Dsm_platform_handler.c38 vaddr_t reg = 0; in oem_sysreg() local
45 reg = core_mmu_get_va(addr, MEM_AREA_IO_SEC, sizeof(uint32_t)); in oem_sysreg()
50 if (!reg || !mask) in oem_sysreg()
52 PRIx32" (0x%"PRIxVA")", *pvalue, addr, reg); in oem_sysreg()
54 io_write32(reg, *pvalue); in oem_sysreg()
56 io_mask32(reg, *pvalue, mask); in oem_sysreg()
59 if (!reg || !auth->rmask) in oem_sysreg()
61 PRIxVA")", addr, reg); in oem_sysreg()
63 *pvalue = io_read32(reg) & auth->rmask; in oem_sysreg()
/optee_os-3.20.0/lib/libutils/ext/arch/arm/
A Dmcount_a64.S19 .macro get_pc reg
20 ldr \reg, [x29, #8]
21 sub \reg, \reg, #4
25 .macro get_lr_addr reg
26 ldr \reg, [x29]
27 add \reg, \reg, #8
/optee_os-3.20.0/core/arch/arm/plat-imx/
A Dimx-common.c17 #define SOC_TYPE(reg) (((reg) & (0x00FF0000)) >> 16) argument
18 #define SOC_REV_MAJOR(reg) (((reg) & (0x0000FF00)) >> 8) argument
19 #define SOC_REV_MINOR(reg) ((reg) & (0x0000000F)) argument
20 #define SOC_REV_MINOR_MX7(reg) ((reg) & (0x000000FF)) argument
/optee_os-3.20.0/core/arch/arm/plat-imx/drivers/
A Dimx_caam.c20 uint32_t reg; in init_caam() local
45 reg = io_read32((vaddr_t)&caam->jr[i].jrmidr_ms); in init_caam()
46 reg |= JROWN_NS | JROWN_MID; in init_caam()
47 io_write32((vaddr_t)&caam->jr[i].jrmidr_ms, reg); in init_caam()
/optee_os-3.20.0/core/arch/arm/kernel/
A Dcache_helpers_a32.S16 .macro dcache_line_size reg, tmp
19 mov \reg, #CTR_WORD_SIZE
20 lsl \reg, \reg, \tmp
23 .macro icache_line_size reg, tmp
26 mov \reg, #CTR_WORD_SIZE
27 lsl \reg, \reg, \tmp
33 .macro do_dcache_maintenance_by_mva reg
38 loop_\reg:
39 write_\reg r0
42 blo loop_\reg
/optee_os-3.20.0/lib/libutee/include/
A Darm64_user_sysreg.h15 #define DEFINE_REG_READ_FUNC_(reg, type, asmreg) \ argument
16 static inline __noprof type read_##reg(void) \
24 #define DEFINE_REG_WRITE_FUNC_(reg, type, asmreg) \ argument
25 static inline __noprof void write_##reg(type val) \
/optee_os-3.20.0/core/drivers/
A Dls_i2c.c175 uint8_t reg = 0; in i2c_bus_test_bus_busy() local
178 reg = io_read8((vaddr_t)&regs->ibsr); in i2c_bus_test_bus_busy()
180 if (reg & I2C_IBSR_IBAL) { in i2c_bus_test_bus_busy()
181 io_write8((vaddr_t)&regs->ibsr, reg); in i2c_bus_test_bus_busy()
208 uint8_t reg = 0; in i2c_transfer_complete() local
211 reg = io_read8((vaddr_t)&regs->ibsr); in i2c_transfer_complete()
213 if (reg & I2C_IBSR_IBIF) { in i2c_transfer_complete()
227 if (reg & I2C_IBSR_TCF) in i2c_transfer_complete()
328 uint8_t reg = 0; in i2c_stop() local
330 reg = io_read8((vaddr_t)&regs->ibsr); in i2c_stop()
[all …]
/optee_os-3.20.0/core/kernel/
A Ddt.c172 const void *reg; in _fdt_reg_base_address() local
181 reg = fdt_getprop(fdt, offs, "reg", &len); in _fdt_reg_base_address()
182 if (!reg) in _fdt_reg_base_address()
189 return _fdt_read_paddr(reg, ncells); in _fdt_reg_base_address()
194 const uint32_t *reg; in _fdt_reg_size() local
205 if (!reg) in _fdt_reg_size()
212 reg += n; in _fdt_reg_size()
218 sz = fdt32_to_cpu(*reg); in _fdt_reg_size()
222 reg++; in _fdt_reg_size()
223 sz = fdt32_to_cpu(*reg); in _fdt_reg_size()
[all …]
/optee_os-3.20.0/core/drivers/crypto/caam/include/
A Dcaam_desc_defines.h65 #define LOAD_DST(reg) SHIFT_U32((reg) & 0x7F, 16) argument
80 #define STORE_SRC(reg) SHIFT_U32((reg) & 0x7F, 16) argument
144 #define FIFO_LOAD_INPUT(reg) SHIFT_U32((FIFO_LOAD_##reg) & 0x3F, 16) argument
243 #define MOVE_REG_SRC(reg) SHIFT_U32((reg) & 0xF, 20) argument
495 #define MATH_SRC0(reg) SHIFT_U32((MATH_SRC0_##reg) & 0xF, 16) argument
509 #define MATH_SRC1(reg) SHIFT_U32((MATH_SRC1_##reg) & 0xF, 12) argument
523 #define MATH_DST(reg) SHIFT_U32((MATH_DST_##reg) & 0xF, 8) argument
538 #define MATHI_SRC(reg) SHIFT_U32((MATH_SRC0_##reg) & 0xF, 16) argument
539 #define MATHI_DST(reg) SHIFT_U32((MATH_DST_##reg) & 0xF, 12) argument
584 #define PKHA_REG_SRC(reg) SHIFT_U32((PKHA_REG_##reg) & 0x7, 17) argument
[all …]

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