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Searched refs:register_dynamic_shm (Results 1 – 6 of 6) sorted by relevance

/optee_os-3.20.0/core/arch/arm/plat-rzg/
A Dmain.c18 register_dynamic_shm(NSEC_DDR_0_BASE, NSEC_DDR_0_SIZE);
20 register_dynamic_shm(NSEC_DDR_1_BASE, NSEC_DDR_1_SIZE);
23 register_dynamic_shm(NSEC_DDR_2_BASE, NSEC_DDR_2_SIZE);
26 register_dynamic_shm(NSEC_DDR_3_BASE, NSEC_DDR_3_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-bcm/
A Dmain.c40 register_dynamic_shm(BCM_DRAM0_NS_BASE, BCM_DRAM0_NS_SIZE);
43 register_dynamic_shm(BCM_DRAM1_NS_BASE, BCM_DRAM1_NS_SIZE);
46 register_dynamic_shm(BCM_DRAM2_NS_BASE, BCM_DRAM2_NS_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-hikey/
A Dmain.c36 register_dynamic_shm(DRAM0_BASE, DRAM0_SIZE_NSEC);
38 register_dynamic_shm(DRAM1_BASE, DRAM1_SIZE_NSEC);
41 register_dynamic_shm(DRAM2_BASE, DRAM2_SIZE_NSEC);
/optee_os-3.20.0/core/arch/arm/plat-imx/
A Dmain.c100 register_dynamic_shm(CFG_NSEC_DDR_0_BASE, CFG_NSEC_DDR_0_SIZE);
102 register_dynamic_shm(CFG_NSEC_DDR_1_BASE, CFG_NSEC_DDR_1_SIZE);
/optee_os-3.20.0/core/arch/arm/plat-poplar/
A Dmain.c21 register_dynamic_shm(DRAM0_BASE_NSEC, DRAM0_SIZE_NSEC);
/optee_os-3.20.0/core/include/mm/
A Dcore_mmu.h223 #define register_dynamic_shm(addr, size) \ macro

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