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/optee_os-3.20.0/core/arch/arm/kernel/
A Dentry_a64.S32 ldr w1, [x1]
33 mul x1, x0, x1
189 add x1, x1, x2 /* __data_end + len */
210 add x1, x1, x2
262 sub x1, x1, x0
367 sub x1, x1, x0
398 sub x1, x1, x0
507 orr x1, x1, #SCTLR_M
513 add x1, x1, x6
523 orr x1, x1, #SCTLR_I
[all …]
A Dthread_a64.S70 mov sp, x1
245 add x1, x1, x0
631 sub x1, x1, x0
638 ldr x1, [x1]
644 sub x1, x1, x0
645 br x1
747 add x1, x0, x1
753 cmp x0, x1
798 mov x1, sp
827 ldp x0, x1, [x1, #THREAD_CORE_LOCAL_X0]
[all …]
A Dmisc_a64.S38 ubfx x1, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
39 add x0, x0, x1, LSL #(CFG_CORE_CLUSTER_SHIFT)
46 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
48 add x1, x1, x2, LSL #(CFG_CORE_CLUSTER_SHIFT)
49 add x0, x0, x1, LSL #(CFG_CORE_THREAD_SHIFT)
A Dthread_spmc_a64.S19 mov x1, #FFA_TARGET_INFO_MBZ /* Target info MBZ */
80 mov x1, #0 /* Pass NULL pointer for caller_sp, coming from NW */
107 mrs x1, daif
108 orr x1, x1, #(SPSR_64_MODE_EL1 << SPSR_64_MODE_EL_SHIFT)
113 push x1, x30
121 read_apiakeyhi x1
127 pop x1, xzr /* Match "push x1, x30" above */
177 mov x1, #THREAD_CTX_SIZE
179 madd x1, x1, x0, x2
180 ldr w1, [x1, #THREAD_CTX_TSD_RPC_TARGET_INFO]
A Dcache_helpers_a64.S30 add x1, x0, x1
36 cmp x0, x1
110 lsr x1, x0, x2 // extract cache type bits from clidr
111 and x1, x1, #7 // mask the bits for current cache only
112 cmp x1, #2 // see what cache we have at this level
117 mrs x1, ccsidr_el1 // read the new ccsidr
118 and x2, x1, #7 // extract the length of the cache lines
120 ubfx x4, x1, #3, #10 // maximum way number
228 add x1, x0, x1
234 cmp x0, x1
A Dthread_optee_smc_a64.S82 mov x1, x0
92 mov x1, x0
102 mov x1, x0
112 mov x1, x0
122 mov x1, x0
132 mov x1, x0
183 mrs x1, daif
184 orr x1, x1, #(SPSR_64_MODE_EL1 << SPSR_64_MODE_EL_SHIFT)
189 push x1, x30
197 read_apiakeyhi x1
[all …]
A Dspin_lock_a64.S76 mov x1, x0
78 .loop: ldaxr w0, [x1]
80 stxr w0, w2, [x1]
/optee_os-3.20.0/core/arch/arm/plat-d06/
A Dcore_pos_a64.S22 lsr x1, x0, 8
23 and x2, x1, 0x7
25 lsr x1, x0, 16
26 and x3, x1, 0x7
28 lsr x1, x0, 20
29 and x4, x1, 0x7
/optee_os-3.20.0/core/arch/arm/plat-rcar/
A Dcore_pos_a64.S32 ubfx x1, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
68 lsl x1, x1, #1
69 2: lsl x1, x1, #1
70 add x0, x0, x1
A Dromapi_call.S25 mov x20, x1
75 mov x1, x21 /* x21: uint64_t arg2 */
/optee_os-3.20.0/core/arch/arm/tee/
A Darch_svc_a64.S17 uint64_t x1;
35 stp x0, x1, [sp, #SC_REC_X0]
57 sub x1, x6, #0x4
58 lsl x1, x1, #3
62 cmp x1, x0
63 csel x0, x1, x0, ge
74 mov x1, x5
115 ldr w3, [x1], #4
177 mov x1, #0 /* panic = false */
192 mov x1, #1 /* panic = true */
A Darch_svc.c396 .x1 = pushed[2], in save_panic_regs_a32_ta()
433 (uaddr_t)regs->x1, in save_panic_stack()
439 (uaddr_t)regs->x1); in save_panic_stack()
448 save_panic_regs_a32_ta(tsd, (uint32_t *)regs->x1); in save_panic_stack()
450 save_panic_regs_a64_ta(tsd, (uint64_t *)regs->x1); in save_panic_stack()
477 regs->x1 = panic; in tee_svc_sys_return_helper()
/optee_os-3.20.0/core/arch/arm/plat-marvell/otx2/
A Dcore_pos.S10 ubfx x1, x0, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
12 mul x1, x1, x2
14 add x0, x1, x2
/optee_os-3.20.0/lib/libutils/ext/arch/arm/
A Dmcount_a64.S47 adjust_pc x1, x30
52 get_lr_addr x1
63 stp x0, x1, [sp]
73 ldp x0, x1, [sp]
/optee_os-3.20.0/core/arch/arm/plat-vexpress/
A Djuno_core_pos_a64.S12 and x1, x0, #MPIDR_CPU_MASK
15 add x0, x1, x0, LSR #6
/optee_os-3.20.0/lib/libutee/arch/arm/
A Dutee_syscalls_a64.S21 stp x0, x1, [sp, #16]
27 ldp x0, x1, [sp, #16]
42 mov x1, sp
/optee_os-3.20.0/core/lib/libtomcrypt/src/ciphers/
A Didea.c104 ushort16 x0, x1, x2, x3, t0, t1; in s_process_block() local
107 LOAD16(x1, in + 2); in s_process_block()
113 x1 += m_key[i*6+1]; in s_process_block()
118 t1 = t0 + (x1^x3); in s_process_block()
123 t0 ^= x1; in s_process_block()
124 x1 = x2^t1; in s_process_block()
130 x1 += m_key[LTC_IDEA_ROUNDS*6+2]; in s_process_block()
135 STORE16(x1, out + 4); in s_process_block()
/optee_os-3.20.0/core/lib/libtomcrypt/src/stream/sosemanuk/
A Dsosemanuk.c175 #define SERPENT_LT(x0, x1, x2, x3) do { \ argument
178 x1 = x1 ^ x0 ^ x2; \
180 x1 = ROLc(x1, 1); \
182 x0 = x0 ^ x1 ^ x3; \
183 x2 = x2 ^ x3 ^ T32(x1 << 7); \
337 #define KA(zc, x0, x1, x2, x3) do { \ in sosemanuk_setiv() argument
339 x1 ^= st->kc[(zc) + 1]; \ in sosemanuk_setiv()
610 tt = XMUX(r1, s ## x1, s ## x8); \ in s_sosemanuk_internal()
640 FSM(x0, x1, x2, x3, x4, x5, x6, x7, x8, x9); \ in s_sosemanuk_internal()
651 #define SRD(S, x0, x1, x2, x3, ooff) do { \ in s_sosemanuk_internal() argument
[all …]
/optee_os-3.20.0/core/arch/arm/crypto/
A Daes_modes_armv8a_ce_a64.S231 ld1 {v0.16b}, [x1]
266 ld1 {v0.16b}, [x1], #16 /* get next pt block */
305 ld1 {v0.16b}, [x1], #16 /* get next ct block */
343 ld1 {v0.16b}, [x1], #16 /* get next pt block */
374 sub x1, x1, #16
377 ld1 {v7.16b}, [x1], #16 /* reload 1 ct block */
386 ld1 {v1.16b}, [x1], #16 /* get next ct block */
461 ld1 {v3.16b}, [x1], #16
555 ld1 {v1.16b}, [x1], #16
636 ld1 {v1.16b}, [x1], #16
[all …]
A Dsha512_armv8a_ce_a64.S115 0: ld1 {v12.2d-v15.2d}, [x1], #64
116 ld1 {v16.2d-v19.2d}, [x1], #64
/optee_os-3.20.0/core/arch/arm/dts/
A Dstm32mp151.dtsi132 dmas = <&dmamux1 18 0x400 0x1>,
133 <&dmamux1 19 0x400 0x1>,
134 <&dmamux1 20 0x400 0x1>,
135 <&dmamux1 21 0x400 0x1>,
136 <&dmamux1 22 0x400 0x1>;
165 dmas = <&dmamux1 23 0x400 0x1>,
166 <&dmamux1 24 0x400 0x1>,
167 <&dmamux1 25 0x400 0x1>,
168 <&dmamux1 26 0x400 0x1>,
1605 reg = <0x0 0x1>;
[all …]
/optee_os-3.20.0/lib/libutils/isoc/arch/arm/
A Dsetjmp_a64.S78 stp x0, x1, [sp, #-16]!
84 ldp x0, x1, [sp], #16
/optee_os-3.20.0/ldelf/
A Dsyscalls_a64.S26 mov x1, sp
/optee_os-3.20.0/core/arch/arm/include/kernel/
A Dthread_arch.h139 uint64_t x1; /* r1_usr */ member
198 uint64_t x1; /* r1_usr */ member
/optee_os-3.20.0/core/crypto/
A Dsm4.c118 static uint32_t sm4F(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3, in sm4F() argument
121 return x0 ^ sm4Lt(x1 ^ x2 ^ x3 ^ rk); in sm4F()

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