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/optee_os-3.20.0/core/lib/libtomcrypt/src/ciphers/
A Drc2.c166 x10 = (x10 + (x32 & ~x76) + (x54 & x76) + xkey[4*i+0]) & 0xFFFF; in s_rc2_ecb_encrypt()
167 x10 = ((x10 << 1) | (x10 >> 15)); in s_rc2_ecb_encrypt()
169 x32 = (x32 + (x54 & ~x10) + (x76 & x10) + xkey[4*i+1]) & 0xFFFF; in s_rc2_ecb_encrypt()
179 x10 = (x10 + xkey[x76 & 63]) & 0xFFFF; in s_rc2_ecb_encrypt()
186 ct[0] = (unsigned char)x10; in s_rc2_ecb_encrypt()
229 unsigned x76, x54, x32, x10; in s_rc2_ecb_decrypt() local
249 x10 = (x10 - xkey[x76 & 63]) & 0xFFFF; in s_rc2_ecb_decrypt()
259 x32 = (x32 - ((x54 & ~x10) + (x76 & x10) + xkey[4*i+1])) & 0xFFFF; in s_rc2_ecb_decrypt()
261 x10 = ((x10 << 15) | (x10 >> 1)); in s_rc2_ecb_decrypt()
262 x10 = (x10 - ((x32 & ~x76) + (x54 & x76) + xkey[4*i+0])) & 0xFFFF; in s_rc2_ecb_decrypt()
[all …]
/optee_os-3.20.0/core/arch/arm/kernel/
A Dcache_helpers_a64.S97 mov x10, xzr
109 add x2, x10, x10, lsr #1 // work out 3x current cache level
115 msr csselr_el1, x10 // select current cache level in csselr
148 add x10, x10, #2 // increment cache number
149 cmp x3, x10
179 sub x10, x3, #2
A Dabort.c186 ai->regs->x10, ai->regs->x11); in __print_abort_info()
A Dldelf_loader.c254 arg->arm32.regs[10] = tsd->abort_regs.x10; in ldelf_dump_state()
/optee_os-3.20.0/core/arch/arm/plat-rcar/
A Dromapi_call.S38 ldr x10, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET
39 add x9, x9, x10
51 ldr x10, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET
52 add x9, x9, x10
/optee_os-3.20.0/core/arch/arm/dts/
A Dstm32mp131.dtsi168 st,syscfg-fmp = <&syscfg 0x4 0x10>;
205 reg = <0x10 0x4>;
230 reg = <0x170 0x10>;
A Dstm32mp151.dtsi558 st,syscfg-fmp = <&syscfg 0x4 0x10>;
839 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
871 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
902 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
1150 reg = <0x50001000 0x10>;
1288 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1611 reg = <0x10 0x4>;
A Dsama5d2.dtsi679 reg = <0xf8048000 0x10>;
687 reg = <0xf8048010 0x10>;
698 reg = <0xf8048030 0x10>;
705 reg = <0xf8048040 0x10>;
A Dfsl-lx2160a.dtsi1363 reg = <0x10>;
/optee_os-3.20.0/core/arch/arm/include/kernel/
A Dthread_arch.h148 uint64_t x10; /* r10_usr */ member
207 uint64_t x10; /* r10_usr */ member
/optee_os-3.20.0/core/arch/arm/crypto/
A Dghash-ce-core_a64.S432 ldr x10, [sp]
433 ld1 {KS0.16b-KS1.16b}, [x10]
577 st1 {KS0.16b-KS1.16b}, [x10]
/optee_os-3.20.0/core/arch/arm/tee/
A Darch_svc.c405 .x10 = pushed[11], in save_panic_regs_a32_ta()

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