1 /* 2 * Copyright 2014, General Dynamics C4 Systems 3 * 4 * SPDX-License-Identifier: GPL-2.0-only 5 */ 6 7 #pragma once 8 9 #include <machine/interrupt.h> 10 11 #define PIC_IRQ_LINES 16 12 #define IOAPIC_IRQ_LINES 24 13 14 /* interrupt vectors (corresponds to IDT entries) */ 15 16 #define IRQ_INT_OFFSET 0x20 17 #define IRQ_CNODE_SLOT_BITS 8 18 19 typedef enum _interrupt_t { 20 int_invalid = -1, 21 int_debug = 1, 22 int_software_break_request = 3, 23 int_unimpl_dev = 7, 24 int_gp_fault = 13, 25 int_page_fault = 14, 26 int_irq_min = IRQ_INT_OFFSET, /* First IRQ. */ 27 int_irq_isa_min = IRQ_INT_OFFSET, /* Beginning of PIC IRQs */ 28 int_irq_isa_max = IRQ_INT_OFFSET + PIC_IRQ_LINES - 1, /* End of PIC IRQs */ 29 int_irq_user_min = IRQ_INT_OFFSET + PIC_IRQ_LINES, /* First user available vector */ 30 int_irq_user_max = 155, 31 #ifdef CONFIG_IOMMU 32 int_iommu = 156, 33 #endif 34 int_timer = 157, 35 #ifdef ENABLE_SMP_SUPPORT 36 int_remote_call_ipi = 158, 37 int_reschedule_ipi = 159, 38 int_irq_max = 159, /* int_reschedule_ipi is the max irq */ 39 #else 40 int_irq_max = 157, /* int_timer is the max irq */ 41 #endif 42 int_trap_min, 43 int_trap_max = 254, 44 int_spurious = 255, 45 int_max = 255 46 } interrupt_t; 47 48 typedef enum _platform_irq_t { 49 irq_isa_min = int_irq_isa_min - IRQ_INT_OFFSET, 50 irq_isa_max = int_irq_isa_max - IRQ_INT_OFFSET, 51 irq_user_min = int_irq_user_min - IRQ_INT_OFFSET, 52 irq_user_max = int_irq_user_max - IRQ_INT_OFFSET, 53 #ifdef CONFIG_IOMMU 54 irq_iommu = int_iommu - IRQ_INT_OFFSET, 55 #endif 56 irq_timer = int_timer - IRQ_INT_OFFSET, 57 #ifdef ENABLE_SMP_SUPPORT 58 irq_remote_call_ipi = int_remote_call_ipi - IRQ_INT_OFFSET, 59 irq_reschedule_ipi = int_reschedule_ipi - IRQ_INT_OFFSET, 60 #endif 61 maxIRQ = int_irq_max - IRQ_INT_OFFSET, 62 /* This is explicitly 255, instead of -1 like on some other platforms, to ensure 63 * that comparisons between an irq_t (a uint8_t) and irqInvalid (some kind of signed int) 64 * are well defined and behave as expected */ 65 irqInvalid = 255, 66 } platform_irq_t; 67 68 #define KERNEL_TIMER_IRQ irq_timer 69 #define BIOS_PADDR_START 0x0e0000 70 #define BIOS_PADDR_END 0x100000 71 72 #define BIOS_PADDR_VIDEO_RAM_START 0x000A0000 73 /* The text mode framebuffer exists part way into the video ram region */ 74 #define BIOS_PADDR_VIDEO_RAM_TEXT_MODE_START 0x000B8000 75 #define BIOS_PADDR_IVDEO_RAM_END 0x000C0000 76 77