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/seL4-master/include/drivers/smmu/
A Dsmmuv2.h273 #define ACR_SMTNMB_TLBEN BIT(8)
278 #define CBn_FSR_UUT BIT(8)
279 #define CBn_FSR_ASF BIT(7)
280 #define CBn_FSR_TLBLKF BIT(6)
281 #define CBn_FSR_TLBLMCF BIT(5)
282 #define CBn_FSR_EF BIT(4)
283 #define CBn_FSR_PF BIT(3)
284 #define CBn_FSR_AFF BIT(2)
285 #define CBn_FSR_TF BIT(1)
293 #define CBn_ACTLR_CPRE BIT(1)
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/seL4-master/src/arch/arm/64/model/
A Dstatedata.c21 asid_pool_t *armKSASIDTable[BIT(asidHighBits)];
85 vspace_root_t armKSGlobalUserVSpace[BIT(seL4_VSpaceIndexBits)] ALIGN_BSS(BIT(seL4_VSpaceBits));
86 pgde_t armKSGlobalKernelPGD[BIT(PGD_INDEX_BITS)] ALIGN_BSS(BIT(PGD_SIZE_BITS));
88 pude_t armKSGlobalKernelPUD[BIT(PUD_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PUDBits));
89 pde_t armKSGlobalKernelPDs[BIT(PUD_INDEX_BITS)][BIT(PD_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageDirBits)…
90 pte_t armKSGlobalKernelPT[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
93 pde_t *armKSGlobalLogPDE = &armKSGlobalKernelPDs[BIT(PUD_INDEX_BITS) - 1][BIT(PD_INDEX_BITS) - 2];
97 GET_PD_INDEX(KS_LOG_PPTR) == BIT(PD_INDEX_BITS) - 2);
108 asid_t armKSHWASIDTable[BIT(hwASIDBits)];
116 cte_t smmuStateSIDNode[BIT(SMMU_SID_CNODE_SLOT_BITS)] ALIGN(BIT(SMMU_SID_CNODE_SLOT_BITS + seL4_Slo…
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/seL4-master/include/arch/x86/arch/machine/
A Dcpu_registers.h9 #define CR0_MONITOR_COPROC BIT(1) /* Trap on FPU "WAIT" commands. */
10 #define CR0_EMULATION BIT(2) /* Enable OS emulation of FPU. */
11 #define CR0_TASK_SWITCH BIT(3) /* Trap on any FPU usage, for lazy FPU. */
12 #define CR0_NUMERIC_ERROR BIT(5) /* Internally handle FPU problems. */
15 #define CR4_OSFXSR BIT(9) /* Enable SSE et. al. features. */
16 #define CR4_OSXMMEXCPT BIT(10) /* Enable SSE exceptions. */
17 #define CR4_OSXSAVE BIT(18) /* Enavle XSAVE feature set */
18 #define CR4_VMXE BIT(13) /* Enable VMX mode. */
22 #define FLAGS_TF BIT(8) /* Trap Flag */
23 #define FLAGS_IF BIT(9) /* Interrupt enable Flag */
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/seL4-master/src/arch/x86/64/model/
A Dstatedata.c10 pml4e_t x64KSKernelPML4[BIT(PML4_INDEX_BITS)] ALIGN(BIT(seL4_PML4Bits)) VISIBLE;
11 pdpte_t x64KSKernelPDPT[BIT(PDPT_INDEX_BITS)] ALIGN(BIT(seL4_PDPTBits));
13 pde_t x64KSKernelPD[BIT(PD_INDEX_BITS)] ALIGN(BIT(seL4_PageDirBits));
15 pde_t x64KSKernelPDs[BIT(PDPT_INDEX_BITS)][BIT(PD_INDEX_BITS)] ALIGN(BIT(seL4_PageDirBits));
17 pte_t x64KSKernelPT[BIT(PT_INDEX_BITS)] ALIGN(BIT(seL4_PageTableBits));
20 pml4e_t x64KSSKIMPML4[BIT(PML4_INDEX_BITS)] ALIGN(BIT(seL4_PML4Bits));
21 pdpte_t x64KSSKIMPDPT[BIT(PDPT_INDEX_BITS)] ALIGN(BIT(seL4_PDPTBits));
22 pde_t x64KSSKIMPD[BIT(PD_INDEX_BITS)] ALIGN(BIT(seL4_PageDirBits));
/seL4-master/src/arch/arm/32/model/
A Dstatedata.c18 asid_pool_t *armKSASIDTable[BIT(asidHighBits)];
21 asid_t armKSHWASIDTable[BIT(hwASIDBits)];
26 pde_t armKSGlobalPD[BIT(PD_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageDirBits));
29 pte_t armKSGlobalPT[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
32 pte_t armKSGlobalLogPT[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
37 pdeS1_t armHSGlobalPGD[BIT(PGD_INDEX_BITS)] ALIGN_BSS(BIT(PGD_SIZE_BITS));
39 pdeS1_t armHSGlobalPD[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
41 pteS1_t armHSGlobalPT[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
43 pde_t armUSGlobalPD[BIT(PD_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageDirBits));;
/seL4-master/src/arch/arm/32/
A Dhead.S19 #define CR_ALIGN_SET BIT(CONTROL_U)
20 #define CR_ALIGN_CLEAR BIT(CONTROL_A)
22 #define CR_ALIGN_SET BIT(CONTROL_A)
23 #define CR_ALIGN_CLEAR BIT(CONTROL_U)
27 #define CR_L1_ICACHE_SET BIT(CONTROL_I)
53 BIT(CONTROL_M) | \
55 BIT(CONTROL_V) | \
56 BIT(CONTROL_XP))
62 BIT(CONTROL_B) | \
69 BIT(CONTROL_AP))
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/seL4-master/include/arch/arm/arch/object/
A Dvcpu.h16 #define HCR_RW BIT(31) /* Execution state control */
17 #define HCR_TRVM BIT(30) /* trap reads of VM controls */
18 #define HCR_HCD BIT(29) /* Disable HVC */
19 #define HCR_TDZ BIT(28) /* trap DC ZVA AArch64 only */
20 #define HCR_TGE BIT(27) /* Trap general exceptions */
21 #define HCR_TVM BIT(26) /* Trap MMU access */
22 #define HCR_TTLB BIT(25) /* Trap TLB operations */
23 #define HCR_TPU BIT(24) /* Trap cache maintenance */
24 #define HCR_TPC BIT(23) /* Trap cache maintenance PoC */
25 #define HCR_TSW BIT(22) /* Trap cache maintenance set/way */
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/seL4-master/src/plat/tk1/machine/
A Dsmmu.c22 #define PTB_DATA_READ BIT(31)
23 #define PTB_DATA_WRITE BIT(30)
24 #define PTB_DATA_NONSECURE BIT(29)
27 #define MODULE_ASID_ENABLE BIT(31)
32 #define TLB_ASID_MATCH BIT(31)
69 static char smmu_pds[ARM_PLAT_NUM_SMMU][BIT(SMMU_PD_INDEX_BITS)] ALIGN(BIT(SMMU_PD_INDEX_BITS));
206 smmu_regs->intmask = BIT(MC_APB_ASID_UPDATE_BIT) | BIT(MC_SMMU_PAGE_BIT) | in plat_smmu_init()
207 BIT(MC_DECERR_MTS_BIT) | BIT(MC_SECERR_SEC_BIT) | in plat_smmu_init()
208 BIT(MC_DECERR_VPR_BIT) | BIT(MC_ARBITRATION_EMEM_BIT) | in plat_smmu_init()
209 BIT(MC_SECURITY_BIT) | BIT(MC_DECERR_EMEM_BIT); in plat_smmu_init()
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/seL4-master/include/arch/x86/arch/64/mode/model/
A Dstatedata.h14 extern pml4e_t x64KSKernelPML4[BIT(PML4_INDEX_BITS)] VISIBLE;
15 extern pdpte_t x64KSKernelPDPT[BIT(PDPT_INDEX_BITS)];
17 extern pde_t x64KSKernelPD[BIT(PD_INDEX_BITS)];
19 extern pde_t x64KSKernelPDs[BIT(PDPT_INDEX_BITS)][BIT(PD_INDEX_BITS)];
21 extern pte_t x64KSKernelPT[BIT(PT_INDEX_BITS)];
24 extern pml4e_t x64KSSKIMPML4[BIT(PML4_INDEX_BITS)] ALIGN(BIT(seL4_PML4Bits));
25 extern pdpte_t x64KSSKIMPDPT[BIT(PDPT_INDEX_BITS)] ALIGN(BIT(seL4_PDPTBits));
28 extern pde_t x64KSSKIMPD[BIT(PD_INDEX_BITS)] ALIGN(BIT(seL4_PageDirBits));
/seL4-master/include/arch/arm/arch/32/mode/model/
A Dstatedata.h15 extern asid_pool_t *armKSASIDTable[BIT(asidHighBits)] VISIBLE;
16 extern asid_t armKSHWASIDTable[BIT(hwASIDBits)] VISIBLE;
20 extern pde_t armKSGlobalPD[BIT(PD_INDEX_BITS)] VISIBLE;
21 extern pte_t armKSGlobalPT[BIT(PT_INDEX_BITS)] VISIBLE;
24 extern pte_t armKSGlobalLogPT[BIT(PT_INDEX_BITS)] VISIBLE;
28 extern pdeS1_t armHSGlobalPGD[BIT(PGD_INDEX_BITS)] VISIBLE;
29 extern pdeS1_t armHSGlobalPD[BIT(PT_INDEX_BITS)] VISIBLE;
30 extern pteS1_t armHSGlobalPT[BIT(PT_INDEX_BITS)] VISIBLE;
31 extern pde_t armUSGlobalPD[BIT(PD_INDEX_BITS)] VISIBLE;
34 extern pte_t armUSGlobalPT[BIT(PT_INDEX_BITS)] VISIBLE;
/seL4-master/include/arch/arm/arch/64/mode/model/
A Dstatedata.h20 extern asid_pool_t *armKSASIDTable[BIT(asidHighBits)] VISIBLE;
24 extern vspace_root_t armKSGlobalUserVSpace[BIT(seL4_VSpaceIndexBits)] VISIBLE;
25 extern pgde_t armKSGlobalKernelPGD[BIT(PGD_INDEX_BITS)] VISIBLE;
27 extern pude_t armKSGlobalKernelPUD[BIT(PUD_INDEX_BITS)] VISIBLE;
28 extern pde_t armKSGlobalKernelPDs[BIT(PUD_INDEX_BITS)][BIT(PD_INDEX_BITS)] VISIBLE;
29 extern pte_t armKSGlobalKernelPT[BIT(PT_INDEX_BITS)] VISIBLE;
33 extern asid_t armKSHWASIDTable[BIT(hwASIDBits)] VISIBLE;
44 extern cte_t smmuStateSIDNode[BIT(SMMU_SID_CNODE_SLOT_BITS)];
46 extern cte_t smmuStateCBNode[BIT(SMMU_CB_CNODE_SLOT_BITS)];
/seL4-master/src/arch/riscv/model/
A Dstatedata.c18 asid_pool_t *riscvKSASIDTable[BIT(asidHighBits)];
21 pte_t kernel_root_pageTable[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
24 pte_t kernel_image_level2_pt[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
25 pte_t kernel_image_level2_dev_pt[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
27 pte_t kernel_image_level2_log_buffer_pt[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
/seL4-master/src/plat/bcm2837/machine/
A Dintc.c50 pending &= ~BIT(INTERRUPT_BASIC_IRQ_PENDING_REGISTER1 - BASIC_IRQ_OFFSET); in getActiveIRQ()
78 core_regs->coreTimersIrqCtrl[0] &= ~BIT(irq); in maskInterrupt()
80 core_regs->coreTimersIrqCtrl[0] |= BIT(irq); in maskInterrupt()
88 core_regs->coreMailboxesIrqCtrl[0] &= ~BIT(irq); in maskInterrupt()
90 core_regs->coreMailboxesIrqCtrl[0] |= BIT(irq); in maskInterrupt()
95 core_regs->localTimerCtl &= ~BIT(LOCAL_TIMER_CTRL_IRQ_BIT); in maskInterrupt()
97 core_regs->localTimerCtl |= BIT(LOCAL_TIMER_CTRL_IRQ_BIT); in maskInterrupt()
117 intc_regs->bfDisableBasicIRQs = BIT(irq - BASIC_IRQ_OFFSET); in maskInterrupt()
119 intc_regs->bfEnableBasicIRQs = BIT(irq - BASIC_IRQ_OFFSET); in maskInterrupt()
125 intc_regs->bfDisableIRQs[index] = BIT(normal_irq % 32); in maskInterrupt()
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/seL4-master/src/arch/arm/machine/
A Dl2c_310.c39 #define CTRL_CTRL_EN BIT(0)
85 #define MAINTENANCE_PENDING BIT(0)
88 #define CTRL2_PWR_DYNAMIC_CLK_EN BIT(1)
89 #define CTRL2_PWR_STANDBY_ON BIT(0)
92 #define CTRL2_PFET_DBL_LINEFILL_EN BIT(30)
93 #define CTRL2_PFET_INST_PREFETCH_EN BIT(29)
94 #define CTRL2_PFET_DATA_PREFETCH_EN BIT(28)
95 #define CTRL2_PFET_DBL_LINEFILL_ON_WRAP_EN BIT(27)
96 #define CTRL2_PFET_PREFETCH_DROP_EN BIT(24)
97 #define CTRL2_PFET_INCR_DBL_LINEFILL_EN BIT(23)
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/seL4-master/src/arch/arm/64/
A Dhead.S20 #define CR_ALIGN_CLEAR BIT(CONTROL_A)
22 #define CR_ALIGN_SET BIT(CONTROL_A)
27 #define CR_L1_ICACHE_SET BIT(CONTROL_I)
31 #define CR_L1_ICACHE_CLEAR BIT(CONTROL_I)
35 #define CR_L1_DCACHE_SET BIT(CONTROL_C)
39 #define CR_L1_DCACHE_CLEAR BIT(CONTROL_C)
45 BIT(CONTROL_M))
50 BIT(CONTROL_SA0) | \
51 BIT(CONTROL_EE) | \
52 BIT(CONTROL_E0E))
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/seL4-master/src/drivers/timer/
A Domap3430-timer.c18 #define TIOCP_CFG_SOFTRESET BIT(1)
19 #define TCLR_AUTORELOAD BIT(1)
20 #define TCLR_COMPAREENABLE BIT(6)
21 #define TCLR_STARTTIMER BIT(0)
22 #define TIER_MATCHENABLE BIT(0)
23 #define TIER_OVERFLOWENABLE BIT(1)
28 #define INTCPS_SYSCONFIG_SOFTRESET BIT(1)
29 #define INTCPS_SYSSTATUS_RESETDONE BIT(0)
A Dam335x-timer.c18 #define TIOCP_CFG_SOFTRESET BIT(0)
20 #define TIER_MATCH_ENABLE BIT(0)
21 #define TIER_OVERFLOW_ENABLE BIT(1)
22 #define TIER_COMPARE_ENABLE BIT(2)
24 #define TCLR_STARTTIMER BIT(0)
25 #define TCLR_AUTORELOAD BIT(1)
26 #define TCLR_PRESCALE_ENABLE BIT(5)
27 #define TCLR_COMPAREENABLE BIT(6)
34 #define WDT_WWPS_PEND_WSPR BIT(4)
/seL4-master/src/drivers/serial/
A Dbcm2835-aux-uart.c27 #define MU_LSR_TXEMPTY BIT(5)
30 #define MU_LSR_TXIDLE BIT(6)
31 #define MU_LSR_RXOVERRUN BIT(1)
32 #define MU_LSR_DATAREADY BIT(0)
33 #define MU_LCR_DLAB BIT(7)
34 #define MU_LCR_BREAK BIT(6)
35 #define MU_LCR_DATASIZE BIT(0)
/seL4-master/src/arch/arm/armv/armv8-a/64/
A Duser_access.c11 #define EL0VCTEN BIT(1)
12 #define EL0PCTEN BIT(0)
13 #define EL0VTEN BIT(8)
14 #define EL0PTEN BIT(9)
17 #define EL1PCEN BIT(1)
18 #define EL1PCTEN BIT(0)
20 #define PMUSERENR_EL0_EN BIT(0)
/seL4-master/src/arch/x86/32/model/
A Dstatedata.c14 pde_t ia32KSGlobalPD[BIT(PD_INDEX_BITS)] ALIGN(BIT(seL4_PageDirBits));
15 pte_t ia32KSGlobalPT[BIT(PT_INDEX_BITS)] ALIGN(BIT(seL4_PageTableBits));
18 pte_t ia32KSGlobalLogPT[BIT(PT_INDEX_BITS)] ALIGN(BIT(seL4_PageTableBits));
/seL4-master/src/arch/riscv/machine/
A Dhardware.c44 .end = frame->paddr + BIT(seL4_LargePageBits) in map_kernel_devices()
98 if (sip & BIT(SIP_SEIP)) { in getActiveIRQ()
106 } else if (sip & BIT(SIP_SSIP)) { in getActiveIRQ()
110 } else if (sip & BIT(SIP_STIP)) { in getActiveIRQ()
161 return (sip & (BIT(SIP_STIP) | BIT(SIP_SEIP))); in isIRQPending()
179 clear_sie_mask(BIT(SIE_STIE)); in maskInterrupt()
181 set_sie_mask(BIT(SIE_STIE)); in maskInterrupt()
248 set_sie_mask(BIT(SIE_SEIE) | BIT(SIE_STIE) | SMP_TERNARY(BIT(SIE_SSIE), 0)); in initLocalIRQController()
/seL4-master/include/arch/arm/armv/armv7-a/armv/
A Ddebug.h41 (BIT(5)|BIT(8)|BIT(9)|BIT(13)|BIT(16)|BIT(24)|BIT(29))
78 wcrtmp |= BIT(DBGWCR_BAS_HIGH_SHIFT); in watchpoint8bSupported()
83 return wcrtmp & BIT(DBGWCR_BAS_HIGH_SHIFT); in watchpoint8bSupported()
/seL4-master/include/arch/arm/armv/armv8-a/32/armv/
A Ddebug.h41 (BIT(5)|BIT(8)|BIT(9)|BIT(13)|BIT(16)|BIT(24)|BIT(29))
78 wcrtmp |= BIT(DBGWCR_BAS_HIGH_SHIFT); in watchpoint8bSupported()
83 return wcrtmp & BIT(DBGWCR_BAS_HIGH_SHIFT); in watchpoint8bSupported()
/seL4-master/src/arch/arm/armv/armv8-a/32/
A Duser_access.c11 #define PMUSERENR_ENABLE BIT(0)
13 #define CNTKCTL_PL0PCTEN BIT(0)
14 #define CNTKCTL_PL0VCTEN BIT(1)
15 #define CNTKCTL_PL0VTEN BIT(8)
16 #define CNTKCTL_PL0PTEN BIT(9)
21 #define ID_PFR1_GENERIC_TIMER BIT(16)
/seL4-master/src/arch/arm/armv/armv7-a/
A Duser_access.c11 #define PMUSERENR_ENABLE BIT(0)
13 #define CNTKCTL_PL0PCTEN BIT(0)
14 #define CNTKCTL_PL0VCTEN BIT(1)
15 #define CNTKCTL_PL0VTEN BIT(8)
16 #define CNTKCTL_PL0PTEN BIT(9)
21 #define ID_PFR1_GENERIC_TIMER BIT(16)

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