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Searched refs:CONTROL_I (Results 1 – 4 of 4) sorted by relevance

/seL4-master/src/arch/arm/64/
A Dhead.S27 #define CR_L1_ICACHE_SET BIT(CONTROL_I)
31 #define CR_L1_ICACHE_CLEAR BIT(CONTROL_I)
/seL4-master/src/arch/arm/32/
A Dhead.S27 #define CR_L1_ICACHE_SET BIT(CONTROL_I)
31 #define CR_L1_ICACHE_CLEAR BIT(CONTROL_I)
/seL4-master/include/arch/arm/arch/64/mode/machine/
A Dhardware.h20 #define CONTROL_I 12 /* Instruction access Cacheability control */ macro
/seL4-master/include/arch/arm/arch/32/mode/machine/
A Dhardware.h25 #define CONTROL_I 12 /* L1 instruction cache enable */ macro

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