Searched refs:cores (Results 1 – 8 of 8) sorted by relevance
29 * bootloader (e.g. armstub). It has parked the secondary cores there,33 * placed here. In non-SMP configurations, the cores must keep spinning34 * forever. Re-using this memory will cause the secondary cores to
13 # Note: If we enable the Denver 2 cores, which are 40-bit PA,14 # the 44-bit PA for Cortex-A57 cores would need to be downgraded to 40bit.
33 static inline void ipi_wait(word_t cores) in ipi_wait() argument37 if (__atomic_fetch_add(&ipiSyncBarrier.count, 1, __ATOMIC_ACQ_REL) == cores) { in ipi_wait()
66 "Use logical IDs to broadcast IPI between cores. Not all machines support logical \67 IDs. In xAPIC mode only 8 cores can be addressed using logical IDs."332 other cores retraining the branch predictor even after context switch."
49 # Assume 8 cores max
291 KernelMaxNumNodes MAX_NUM_NODES "Max number of CPU cores to boot"
404 VSpace between MMUs in CPU cores and SMMU used by device transactions. Moreover,
3497 cores = <0xb6>;
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