Searched refs:instruction (Results 1 – 11 of 11) sorted by relevance
/seL4-master/src/arch/arm/armv/armv7-a/ |
A D | cache.c | 41 static inline word_t readCacheSize(int level, bool_t instruction) in readCacheSize() argument 47 asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r"((level << 1) | instruction)); in readCacheSize()
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/seL4-master/src/arch/arm/armv/armv8-a/64/ |
A D | cache.c | 37 static inline word_t readCacheSize(int level, bool_t instruction) in readCacheSize() argument 43 MSR("csselr_el1", ((level << 1) | instruction)); in readCacheSize()
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/seL4-master/src/arch/arm/armv/armv8-a/32/ |
A D | cache.c | 41 static inline word_t readCacheSize(int level, bool_t instruction) in readCacheSize() argument 47 asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r"((level << 1) | instruction)); in readCacheSize()
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/seL4-master/ |
A D | config.cmake | 497 Only needed on platforms which lack a builtin instruction." 503 Only needed on platforms which lack a builtin instruction." 509 Only needed on platforms which lack a builtin instruction." 515 Only needed on platforms which lack a builtin instruction."
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/seL4-master/src/arch/x86/32/ |
A D | traps.S | 464 movl (4 * NextIP)(%esp), %ebx # EBX contains EIP of the exception generating instruction 515 # EDX : user EIP (pointing to the sysenter instruction)
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/seL4-master/manual/parts/ |
A D | threads.tex | 46 …pifunc{seL4\_TCB\_WriteRegisters}{tcb_writeregisters} with an initial stack pointer and instruction 444 Breakpoints, watchpoints, trace-events and instruction-performance sampling 465 Cortex~A7 for example, there are 6 exclusive instruction breakpoint registers, 468 The instruction breakpoint registers will always be assigned the lower API-IDs, 477 capable of generating a fault \textbf{only} on instruction execution. Currently this will be 479 in \texttt{seL4\_FirstBreakpoint}. If there are no instruction-break exclusive 492 supports both instruction and data breaks. Currently this will be set only on 505 \reg{Breakpoint instruction address} & \ipcbloc{IPCBuffer[0]} \\ 524 an instruction breakpoint, to use when setting up the single-stepping 557 \reg{Breakpoint instruction address} & \texttt{num\_instructions} to skip & \ipcbloc{IPCBuffer[0]} … [all …]
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A D | api.tex | 75 that the breakpoint should occur on instruction execution at the specified 103 breakpoint, whether instruction execution, or data access;
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A D | io.tex | 140 appropriate action and restart the thread at the faulting instruction.
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/seL4-master/src/arch/arm/ |
A D | config.cmake | 57 "Do not enable the L1 instruction cache on startup for debugging purposes." 216 # the L1 instruction on the Cortex-A72 cache has a 64-byte cache line.
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/seL4-master/src/arch/x86/ |
A D | config.cmake | 156 …XSAVE -> Original XSAVE instruction. This is the only XSAVE instruction that is guaranteed to exis… 162 … XSAVES -> Save state taking advantage of the modified optimization. This instruction is only \
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/seL4-master/src/arch/x86/64/ |
A D | traps.S | 586 # r11, the instruction *AFTER* the syscall is in 628 # RDX : user EIP (pointing to the sysenter instruction)
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