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Searched refs:val (Results 1 – 25 of 38) sorted by relevance

12

/seL4-master/include/arch/x86/arch/32/mode/machine/
A Dcpu_registers.h12 unsigned long val; in read_cr3() local
13 asm volatile("movl %%cr3, %0" : "=r"(val), "=m"(control_reg_order)); in read_cr3()
14 return val; in read_cr3()
17 static inline void write_cr3(unsigned long val) in write_cr3() argument
24 unsigned long val; in read_cr0() local
26 return val; in read_cr0()
29 static inline void write_cr0(unsigned long val) in write_cr0() argument
36 unsigned long val; in read_cr2() local
38 return val; in read_cr2()
43 unsigned long val; in read_cr4() local
[all …]
A Ddebug.h24 static inline void writeDr6Reg(word_t val) in writeDr6Reg() argument
29 : "r"(val)); in writeDr6Reg()
42 static inline void writeDr7Reg(word_t val) in writeDr7Reg() argument
47 : "r"(val)); in writeDr7Reg()
72 static inline void writeDrReg(uint8_t reg, word_t val) in writeDrReg() argument
77 asm volatile("movl %0, %%dr0 \n\t" :: "r"(val)); in writeDrReg()
80 asm volatile("movl %0, %%dr1 \n\t" :: "r"(val)); in writeDrReg()
83 asm volatile("movl %0, %%dr2 \n\t" :: "r"(val)); in writeDrReg()
86 asm volatile("movl %0, %%dr3 \n\t" :: "r"(val)); in writeDrReg()
/seL4-master/include/arch/arm/armv/armv7-a/armv/
A Dvcpu.h45 asm("msr lr_svc, %[val]" :: [val]"r"(val)); in set_lr_svc()
57 asm("msr sp_svc, %[val]" :: [val]"r"(val)); in set_sp_svc()
69 asm("msr spsr_svc, %[val]" :: [val]"r"(val)); in set_spsr_svc()
81 asm("msr lr_abt, %[val]" :: [val]"r"(val)); in set_lr_abt()
93 asm("msr sp_abt, %[val]" :: [val]"r"(val)); in set_sp_abt()
105 asm("msr spsr_abt, %[val]" :: [val]"r"(val)); in set_spsr_abt()
117 asm("msr lr_und, %[val]" :: [val]"r"(val)); in set_lr_und()
129 asm("msr sp_und, %[val]" :: [val]"r"(val)); in set_sp_und()
153 asm("msr lr_irq, %[val]" :: [val]"r"(val)); in set_lr_irq()
165 asm("msr sp_irq, %[val]" :: [val]"r"(val)); in set_sp_irq()
[all …]
A Dbenchmark.h21 word_t val; in armv_enableOverflowIRQ() local
22 MRC(PMINTENSET, val); in armv_enableOverflowIRQ()
23 val |= BIT(CCNT_INDEX); in armv_enableOverflowIRQ()
24 MCR(PMINTENSET, val); in armv_enableOverflowIRQ()
29 word_t val = BIT(CCNT_INDEX); in armv_handleOverflowIRQ() local
30 MCR(PMOVSR, val); in armv_handleOverflowIRQ()
A Ddebug.h33 static inline void writeDscrCp(word_t val) in writeDscrCp() argument
35 MCR(DBGDSCR_ext, val); in writeDscrCp()
/seL4-master/include/arch/arm/armv/armv8-a/32/armv/
A Dvcpu.h45 asm("msr lr_svc, %[val]" :: [val]"r"(val)); in set_lr_svc()
57 asm("msr sp_svc, %[val]" :: [val]"r"(val)); in set_sp_svc()
69 asm("msr spsr_svc, %[val]" :: [val]"r"(val)); in set_spsr_svc()
81 asm("msr lr_abt, %[val]" :: [val]"r"(val)); in set_lr_abt()
93 asm("msr sp_abt, %[val]" :: [val]"r"(val)); in set_sp_abt()
105 asm("msr spsr_abt, %[val]" :: [val]"r"(val)); in set_spsr_abt()
117 asm("msr lr_und, %[val]" :: [val]"r"(val)); in set_lr_und()
129 asm("msr sp_und, %[val]" :: [val]"r"(val)); in set_sp_und()
153 asm("msr lr_irq, %[val]" :: [val]"r"(val)); in set_lr_irq()
165 asm("msr sp_irq, %[val]" :: [val]"r"(val)); in set_sp_irq()
[all …]
A Dbenchmark.h21 word_t val; in armv_enableOverflowIRQ() local
22 MRC(PMINTENSET, val); in armv_enableOverflowIRQ()
23 val |= BIT(CCNT_INDEX); in armv_enableOverflowIRQ()
24 MCR(PMINTENSET, val); in armv_enableOverflowIRQ()
29 word_t val = BIT(CCNT_INDEX); in armv_handleOverflowIRQ() local
30 MCR(PMOVSR, val); in armv_handleOverflowIRQ()
A Ddebug.h33 static inline void writeDscrCp(word_t val) in writeDscrCp() argument
35 MCR(DBGDSCR_ext, val); in writeDscrCp()
/seL4-master/include/arch/x86/arch/64/mode/machine/
A Dcpu_registers.h16 static inline void write_cr3(unsigned long val) in write_cr3() argument
18 asm volatile("movq %0, %%cr3" :: "r"(val), "m"(control_reg_order)); in write_cr3()
23 unsigned long val; in read_cr0() local
25 return val; in read_cr0()
28 static inline void write_cr0(unsigned long val) in write_cr0() argument
30 asm volatile("movq %0, %%cr0" :: "r"(val), "m"(control_reg_order)); in write_cr0()
35 unsigned long val; in read_cr2() local
37 return val; in read_cr2()
42 unsigned long val; in read_cr4() local
44 return val; in read_cr4()
[all …]
A Ddebug.h25 static inline void writeDr6Reg(word_t val) in writeDr6Reg() argument
30 : "r"(val)); in writeDr6Reg()
43 static inline void writeDr7Reg(word_t val) in writeDr7Reg() argument
48 : "r"(val)); in writeDr7Reg()
73 static inline void writeDrReg(uint8_t reg, word_t val) in writeDrReg() argument
78 asm volatile("movq %0, %%dr0 \n\t" :: "r"(val)); in writeDrReg()
81 asm volatile("movq %0, %%dr1 \n\t" :: "r"(val)); in writeDrReg()
84 asm volatile("movq %0, %%dr2 \n\t" :: "r"(val)); in writeDrReg()
87 asm volatile("movq %0, %%dr3 \n\t" :: "r"(val)); in writeDrReg()
/seL4-master/src/arch/arm/armv/armv8-a/64/
A Duser_access.c27 MSR("PMUSERENR_EL0", val); in check_export_pmu()
33 uint32_t val = 0; in check_export_arch_timer() local
35 val |= EL0PCTEN; in check_export_arch_timer()
38 val |= EL0PTEN; in check_export_arch_timer()
41 val |= EL0VCTEN; in check_export_arch_timer()
44 val |= EL0VTEN; in check_export_arch_timer()
46 MSR("CNTKCTL_EL1", val); in check_export_arch_timer()
49 val = 0; in check_export_arch_timer()
51 val |= EL1PCTEN; in check_export_arch_timer()
54 val |= EL1PCEN; in check_export_arch_timer()
[all …]
/seL4-master/include/arch/arm/armv/armv8-a/64/armv/
A Dbenchmark.h21 uint32_t val; in armv_enableOverflowIRQ() local
22 MRS(PMINTENSET, val); in armv_enableOverflowIRQ()
23 val |= BIT(CCNT_INDEX); in armv_enableOverflowIRQ()
24 MSR(PMINTENSET, val); in armv_enableOverflowIRQ()
29 uint32_t val = BIT(CCNT_INDEX); in armv_handleOverflowIRQ() local
30 MSR(PMOVSR, val); in armv_handleOverflowIRQ()
/seL4-master/include/arch/arm/arch/32/mode/
A Dmachine.h152 word_t val = 0; in readTTBR0() local
153 asm volatile("mrc p15, 0, %0, c2, c0, 0":"=r"(val):); in readTTBR0()
154 return val; in readTTBR0()
157 static inline void writeTTBR0(word_t val) in writeTTBR0() argument
159 asm volatile("mcr p15, 0, %0, c2, c0, 0":: "r"(val)); in writeTTBR0()
172 word_t val = 0; in readTTBR1() local
174 return val; in readTTBR1()
177 static inline void writeTTBR1(word_t val) in writeTTBR1() argument
185 word_t val = 0; in readTTBCR() local
187 return val; in readTTBCR()
[all …]
/seL4-master/src/arch/arm/machine/
A Dgic_v3.c80 uint32_t val; in gicv3_do_wait_for_rwp() local
89 val = *ctlr_addr; in gicv3_do_wait_for_rwp()
90 if (!(val & GICD_CTLR_RWP)) { in gicv3_do_wait_for_rwp()
98 val = *ctlr_addr; in gicv3_do_wait_for_rwp()
105 } else if (!(val & GICD_CTLR_RWP)) { in gicv3_do_wait_for_rwp()
125 uint32_t val = 0; in gicv3_enable_sre() local
128 SYSTEM_READ_WORD(ICC_SRE_EL1, val); in gicv3_enable_sre()
129 val |= GICC_SRE_EL1_SRE; in gicv3_enable_sre()
131 SYSTEM_WRITE_WORD(ICC_SRE_EL1, val); in gicv3_enable_sre()
185 uint32_t val; in gicr_locate_interface() local
[all …]
A Ddebug.c236 _name(uint16_t bp_num, word_t val) \
240 MCR(MAKE_ ## _reg(1), val); \
243 MCR(MAKE_ ## _reg(2), val); \
246 MCR(MAKE_ ## _reg(3), val); \
249 MCR(MAKE_ ## _reg(4), val); \
252 MCR(MAKE_ ## _reg(5), val); \
255 MCR(MAKE_ ## _reg(6), val); \
258 MCR(MAKE_ ## _reg(7), val); \
261 MCR(MAKE_ ## _reg(8), val); \
264 MCR(MAKE_ ## _reg(9), val); \
[all …]
/seL4-master/include/drivers/irq/
A Driscv_plic0.h74 static inline void writel(uint32_t val, uint64_t addr) in writel() argument
76 *((volatile uint32_t *)(addr)) = val; in writel()
137 uint32_t val = 0; in plic_mask_irq() local
144 val = readl(addr); in plic_mask_irq()
146 val &= ~BIT(bit); in plic_mask_irq()
148 val |= BIT(bit); in plic_mask_irq()
150 writel(val, addr); in plic_mask_irq()
/seL4-master/src/arch/arm/benchmark/
A Dbenchmark.c26 uint32_t val = (BIT(PMCR_ENABLE) | BIT(PMCR_CCNT_RESET) | BIT(PMCR_ECNT_RESET)); in arm_init_ccnt() local
27 SYSTEM_WRITE_WORD(PMCR, val); in arm_init_ccnt()
/seL4-master/include/arch/x86/arch/kernel/
A Dx2apic.h47 static inline void apic_write_reg(apic_reg_t reg, uint32_t val) in apic_write_reg() argument
49 x86_wrmsr(reg, val); in apic_write_reg()
A Dxapic.h48 static inline void apic_write_reg(apic_reg_t reg, uint32_t val) in apic_write_reg() argument
50 *(volatile uint32_t *)(PPTR_APIC + reg) = val; in apic_write_reg()
A Dapic.h22 void apic_write_reg(apic_reg_t reg, uint32_t val);
/seL4-master/src/drivers/timer/
A Dgeneric_timer.c59 uint64_t val; in read_cntpct() local
60 SYSTEM_READ_64(CNTPCT, val); in read_cntpct()
61 return val; in read_cntpct()
/seL4-master/include/arch/arm/arch/machine/
A Dgic_v3.h294 uint32_t val = 0; in getActiveIRQ() local
295 SYSTEM_READ_WORD(ICC_IAR1_EL1, val); in getActiveIRQ()
296 active_irq[CURRENT_CPU_INDEX()] = val; in getActiveIRQ()
317 uint32_t val = 0; in isIRQPending() local
319 SYSTEM_READ_WORD(ICC_HPPIR1_EL1, val); in isIRQPending()
320 return IS_IRQ_VALID(val); in isIRQPending()
/seL4-master/src/
A Dutil.c106 long val = 0; in str_to_long() local
127 val = val * base + res; in str_to_long()
132 return val; in str_to_long()
/seL4-master/src/api/
A Dsyscall.c161 uint64_t val; in handleUnknownSyscall() local
164 val = (uint64_t)getSyscallArg(0, NULL) | ((uint64_t)getSyscallArg(1, NULL) << 32); in handleUnknownSyscall()
166 val = getSyscallArg(0, NULL); in handleUnknownSyscall()
168 x86_wrmsr(reg, val); in handleUnknownSyscall()
171 uint64_t val; in handleUnknownSyscall() local
173 val = x86_rdmsr(reg); in handleUnknownSyscall()
176 setMR(NODE_STATE(ksCurThread), NULL, 0, val & 0xffffffff); in handleUnknownSyscall()
177 setMR(NODE_STATE(ksCurThread), NULL, 1, val >> 32); in handleUnknownSyscall()
180 setMR(NODE_STATE(ksCurThread), NULL, 0, val); in handleUnknownSyscall()
/seL4-master/libsel4/include/sel4/
A Ddeprecated.h100 seL4_ExceptIPC_Set(seL4_Word index, seL4_Word val) in seL4_ExceptIPC_Set() argument
102 seL4_SetMR(index, val); in seL4_ExceptIPC_Set()

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