1 #ifndef _X86_DEBUGREG_H 2 #define _X86_DEBUGREG_H 3 4 5 /* Indicate the register numbers for a number of the specific 6 debug registers. Registers 0-3 contain the addresses we wish to trap on */ 7 8 #define DR_FIRSTADDR 0 9 #define DR_LASTADDR 3 10 #define DR_STATUS 6 11 #define DR_CONTROL 7 12 13 /* Define a few things for the status register. We can use this to determine 14 which debugging register was responsible for the trap. The other bits 15 are either reserved or not of interest to us. */ 16 17 #define DR_TRAP0 (0x1) /* db0 */ 18 #define DR_TRAP1 (0x2) /* db1 */ 19 #define DR_TRAP2 (0x4) /* db2 */ 20 #define DR_TRAP3 (0x8) /* db3 */ 21 #define DR_STEP (0x4000) /* single-step */ 22 #define DR_SWITCH (0x8000) /* task switch */ 23 #define DR_NOT_RTM (0x10000) /* clear: #BP inside RTM region */ 24 #define DR_STATUS_RESERVED_ZERO (~0xffffeffful) /* Reserved, read as zero */ 25 #define DR_STATUS_RESERVED_ONE 0xffff0ff0ul /* Reserved, read as one */ 26 27 /* Now define a bunch of things for manipulating the control register. 28 The top two bytes of the control register consist of 4 fields of 4 29 bits - each field corresponds to one of the four debug registers, 30 and indicates what types of access we trap on, and how large the data 31 field is that we are looking at */ 32 33 #define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */ 34 #define DR_CONTROL_SIZE 4 /* 4 control bits per register */ 35 36 #define DR_RW_EXECUTE (0x0) /* Settings for the access types to trap on */ 37 #define DR_RW_WRITE (0x1) 38 #define DR_IO (0x2) 39 #define DR_RW_READ (0x3) 40 41 #define DR_LEN_1 (0x0) /* Settings for data length to trap on */ 42 #define DR_LEN_2 (0x4) 43 #define DR_LEN_4 (0xC) 44 #define DR_LEN_8 (0x8) 45 46 /* The low byte to the control register determine which registers are 47 enabled. There are 4 fields of two bits. One bit is "local", meaning 48 that the processor will reset the bit after a task switch and the other 49 is global meaning that we have to explicitly reset the bit. */ 50 51 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit */ 52 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */ 53 #define DR_ENABLE_SIZE 2 /* 2 enable bits per register */ 54 55 #define DR_LOCAL_ENABLE_MASK (0x55) /* Set local bits for all 4 regs */ 56 #define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */ 57 58 #define DR7_ACTIVE_MASK (DR_LOCAL_ENABLE_MASK|DR_GLOBAL_ENABLE_MASK) 59 60 /* The second byte to the control register has a few special things. 61 We can slow the instruction pipeline for instructions coming via the 62 gdt or the ldt if we want to. I am not sure why this is an advantage */ 63 64 #define DR_CONTROL_RESERVED_ZERO (~0xffff27fful) /* Reserved, read as zero */ 65 #define DR_CONTROL_RESERVED_ONE (0x00000400ul) /* Reserved, read as one */ 66 #define DR_LOCAL_EXACT_ENABLE (0x00000100ul) /* Local exact enable */ 67 #define DR_GLOBAL_EXACT_ENABLE (0x00000200ul) /* Global exact enable */ 68 #define DR_RTM_ENABLE (0x00000800ul) /* RTM debugging enable */ 69 #define DR_GENERAL_DETECT (0x00002000ul) /* General detect enable */ 70 71 #define write_debugreg(reg, val) do { \ 72 unsigned long __val = val; \ 73 asm volatile ( "mov %0,%%db" #reg : : "r" (__val) ); \ 74 } while (0) 75 #define read_debugreg(reg) ({ \ 76 unsigned long __val; \ 77 asm volatile ( "mov %%db" #reg ",%0" : "=r" (__val) ); \ 78 __val; \ 79 }) 80 long set_debugreg(struct vcpu *, unsigned int reg, unsigned long value); 81 void activate_debugregs(const struct vcpu *); 82 83 #endif /* _X86_DEBUGREG_H */ 84