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Searched refs:GICD_ISENABLERN (Results 1 – 3 of 3) sorted by relevance

/xen-4.10.0-shim-comet/xen/include/asm-arm/
A Dgic.h30 #define GICD_ISENABLERN (0x17C) macro
/xen-4.10.0-shim-comet/xen/arch/arm/
A Dvgic-v2.c224 case VRANGE32(GICD_ISENABLER, GICD_ISENABLERN): in vgic_v2_distr_mmio_read()
451 case VRANGE32(GICD_ISENABLER, GICD_ISENABLERN): in vgic_v2_distr_mmio_write()
A Dvgic-v3.c690 case VRANGE32(GICD_ISENABLER, GICD_ISENABLERN): in __vgic_v3_distr_common_mmio_read()
786 case VRANGE32(GICD_ISENABLER, GICD_ISENABLERN): in __vgic_v3_distr_common_mmio_write()
1192 case VRANGE32(GICD_ISENABLER, GICD_ISENABLERN): in vgic_v3_distr_mmio_read()
1380 case VRANGE32(GICD_ISENABLER, GICD_ISENABLERN): in vgic_v3_distr_mmio_write()

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