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Searched refs:GICD_SETSPI_SR (Results 1 – 2 of 2) sorted by relevance

/xen-4.10.0-shim-comet/xen/include/asm-arm/
A Dgic_v3_defs.h29 #define GICD_SETSPI_SR (0x050) macro
/xen-4.10.0-shim-comet/xen/arch/arm/
A Dvgic-v3.c1177 case VREG32(GICD_SETSPI_SR): in vgic_v3_distr_mmio_read()
1365 case VREG32(GICD_SETSPI_SR): in vgic_v3_distr_mmio_write()

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