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Searched refs:GIC_BASER_CACHE_SameAsInner (Results 1 – 5 of 5) sorted by relevance

/xen-4.10.0-shim-comet/xen/include/asm-arm/
A Dgic_v3_defs.h112 #define GIC_BASER_CACHE_SameAsInner 0ULL macro
/xen-4.10.0-shim-comet/xen/arch/arm/
A Dgic-v3-lpi.c244 val |= GIC_BASER_CACHE_SameAsInner << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT; in gicv3_lpi_allocate_pendtable()
286 reg |= GIC_BASER_CACHE_SameAsInner << GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT; in gicv3_lpi_set_proptable()
A Dgic-v3-its.c306 reg |= GIC_BASER_CACHE_SameAsInner << GITS_BASER_OUTER_CACHEABILITY_SHIFT; in its_map_cbaser()
357 attr |= GIC_BASER_CACHE_SameAsInner << GITS_BASER_OUTER_CACHEABILITY_SHIFT; in its_map_baser()
A Dvgic-v3-its.c1226 case GIC_BASER_CACHE_SameAsInner: in sanitize_its_base_reg()
1471 base_attr |= GIC_BASER_CACHE_SameAsInner << GITS_BASER_OUTER_CACHEABILITY_SHIFT; in vgic_v3_its_init_virtual()
A Dvgic-v3.c404 case GIC_BASER_CACHE_SameAsInner: in vgic_sanitise_outer_cacheability()

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