1 /* 2 * Permission is hereby granted, free of charge, to any person obtaining a copy 3 * of this software and associated documentation files (the "Software"), to 4 * deal in the Software without restriction, including without limitation the 5 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 6 * sell copies of the Software, and to permit persons to whom the Software is 7 * furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice shall be included in 10 * all copies or substantial portions of the Software. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 15 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 16 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 17 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 18 * DEALINGS IN THE SOFTWARE. 19 * 20 * Copyright (c) 2007, Keir Fraser 21 */ 22 23 #ifndef __XEN_PUBLIC_HVM_PARAMS_H__ 24 #define __XEN_PUBLIC_HVM_PARAMS_H__ 25 26 #include "hvm_op.h" 27 28 /* 29 * Parameter space for HVMOP_{set,get}_param. 30 */ 31 32 #define HVM_PARAM_CALLBACK_IRQ 0 33 #define HVM_PARAM_CALLBACK_IRQ_TYPE_MASK xen_mk_ullong(0xFF00000000000000) 34 /* 35 * How should CPU0 event-channel notifications be delivered? 36 * 37 * If val == 0 then CPU0 event-channel notifications are not delivered. 38 * If val != 0, val[63:56] encodes the type, as follows: 39 */ 40 41 #define HVM_PARAM_CALLBACK_TYPE_GSI 0 42 /* 43 * val[55:0] is a delivery GSI. GSI 0 cannot be used, as it aliases val == 0, 44 * and disables all notifications. 45 */ 46 47 #define HVM_PARAM_CALLBACK_TYPE_PCI_INTX 1 48 /* 49 * val[55:0] is a delivery PCI INTx line: 50 * Domain = val[47:32], Bus = val[31:16] DevFn = val[15:8], IntX = val[1:0] 51 */ 52 53 #if defined(__i386__) || defined(__x86_64__) 54 #define HVM_PARAM_CALLBACK_TYPE_VECTOR 2 55 /* 56 * val[7:0] is a vector number. Check for XENFEAT_hvm_callback_vector to know 57 * if this delivery method is available. 58 */ 59 #elif defined(__arm__) || defined(__aarch64__) 60 #define HVM_PARAM_CALLBACK_TYPE_PPI 2 61 /* 62 * val[55:16] needs to be zero. 63 * val[15:8] is interrupt flag of the PPI used by event-channel: 64 * bit 8: the PPI is edge(1) or level(0) triggered 65 * bit 9: the PPI is active low(1) or high(0) 66 * val[7:0] is a PPI number used by event-channel. 67 * This is only used by ARM/ARM64 and masking/eoi the interrupt associated to 68 * the notification is handled by the interrupt controller. 69 */ 70 #define HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_MASK 0xFF00 71 #define HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_LOW_LEVEL 2 72 #endif 73 74 /* 75 * These are not used by Xen. They are here for convenience of HVM-guest 76 * xenbus implementations. 77 */ 78 #define HVM_PARAM_STORE_PFN 1 79 #define HVM_PARAM_STORE_EVTCHN 2 80 81 #define HVM_PARAM_PAE_ENABLED 4 82 83 #define HVM_PARAM_IOREQ_PFN 5 84 85 #define HVM_PARAM_BUFIOREQ_PFN 6 86 #define HVM_PARAM_BUFIOREQ_EVTCHN 26 87 88 #if defined(__i386__) || defined(__x86_64__) 89 90 /* 91 * Viridian enlightenments 92 * 93 * (See http://download.microsoft.com/download/A/B/4/AB43A34E-BDD0-4FA6-BDEF-79EEF16E880B/Hypervisor%20Top%20Level%20Functional%20Specification%20v4.0.docx) 94 * 95 * To expose viridian enlightenments to the guest set this parameter 96 * to the desired feature mask. The base feature set must be present 97 * in any valid feature mask. 98 */ 99 #define HVM_PARAM_VIRIDIAN 9 100 101 /* Base+Freq viridian feature sets: 102 * 103 * - Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) 104 * - APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) 105 * - Virtual Processor index MSR (HV_X64_MSR_VP_INDEX) 106 * - Timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and 107 * HV_X64_MSR_APIC_FREQUENCY) 108 */ 109 #define _HVMPV_base_freq 0 110 #define HVMPV_base_freq (1 << _HVMPV_base_freq) 111 112 /* Feature set modifications */ 113 114 /* Disable timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and 115 * HV_X64_MSR_APIC_FREQUENCY). 116 * This modification restores the viridian feature set to the 117 * original 'base' set exposed in releases prior to Xen 4.4. 118 */ 119 #define _HVMPV_no_freq 1 120 #define HVMPV_no_freq (1 << _HVMPV_no_freq) 121 122 /* Enable Partition Time Reference Counter (HV_X64_MSR_TIME_REF_COUNT) */ 123 #define _HVMPV_time_ref_count 2 124 #define HVMPV_time_ref_count (1 << _HVMPV_time_ref_count) 125 126 /* Enable Reference TSC Page (HV_X64_MSR_REFERENCE_TSC) */ 127 #define _HVMPV_reference_tsc 3 128 #define HVMPV_reference_tsc (1 << _HVMPV_reference_tsc) 129 130 /* Use Hypercall for remote TLB flush */ 131 #define _HVMPV_hcall_remote_tlb_flush 4 132 #define HVMPV_hcall_remote_tlb_flush (1 << _HVMPV_hcall_remote_tlb_flush) 133 134 /* Use APIC assist */ 135 #define _HVMPV_apic_assist 5 136 #define HVMPV_apic_assist (1 << _HVMPV_apic_assist) 137 138 /* Enable crash MSRs */ 139 #define _HVMPV_crash_ctl 6 140 #define HVMPV_crash_ctl (1 << _HVMPV_crash_ctl) 141 142 #define HVMPV_feature_mask \ 143 (HVMPV_base_freq | \ 144 HVMPV_no_freq | \ 145 HVMPV_time_ref_count | \ 146 HVMPV_reference_tsc | \ 147 HVMPV_hcall_remote_tlb_flush | \ 148 HVMPV_apic_assist | \ 149 HVMPV_crash_ctl) 150 151 #endif 152 153 /* 154 * Set mode for virtual timers (currently x86 only): 155 * delay_for_missed_ticks (default): 156 * Do not advance a vcpu's time beyond the correct delivery time for 157 * interrupts that have been missed due to preemption. Deliver missed 158 * interrupts when the vcpu is rescheduled and advance the vcpu's virtual 159 * time stepwise for each one. 160 * no_delay_for_missed_ticks: 161 * As above, missed interrupts are delivered, but guest time always tracks 162 * wallclock (i.e., real) time while doing so. 163 * no_missed_ticks_pending: 164 * No missed interrupts are held pending. Instead, to ensure ticks are 165 * delivered at some non-zero rate, if we detect missed ticks then the 166 * internal tick alarm is not disabled if the VCPU is preempted during the 167 * next tick period. 168 * one_missed_tick_pending: 169 * Missed interrupts are collapsed together and delivered as one 'late tick'. 170 * Guest time always tracks wallclock (i.e., real) time. 171 */ 172 #define HVM_PARAM_TIMER_MODE 10 173 #define HVMPTM_delay_for_missed_ticks 0 174 #define HVMPTM_no_delay_for_missed_ticks 1 175 #define HVMPTM_no_missed_ticks_pending 2 176 #define HVMPTM_one_missed_tick_pending 3 177 178 /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */ 179 #define HVM_PARAM_HPET_ENABLED 11 180 181 /* Identity-map page directory used by Intel EPT when CR0.PG=0. */ 182 #define HVM_PARAM_IDENT_PT 12 183 184 /* Device Model domain, defaults to 0. */ 185 #define HVM_PARAM_DM_DOMAIN 13 186 187 /* ACPI S state: currently support S0 and S3 on x86. */ 188 #define HVM_PARAM_ACPI_S_STATE 14 189 190 /* TSS used on Intel when CR0.PE=0. */ 191 #define HVM_PARAM_VM86_TSS 15 192 193 /* Boolean: Enable aligning all periodic vpts to reduce interrupts */ 194 #define HVM_PARAM_VPT_ALIGN 16 195 196 /* Console debug shared memory ring and event channel */ 197 #define HVM_PARAM_CONSOLE_PFN 17 198 #define HVM_PARAM_CONSOLE_EVTCHN 18 199 200 /* 201 * Select location of ACPI PM1a and TMR control blocks. Currently two locations 202 * are supported, specified by version 0 or 1 in this parameter: 203 * - 0: default, use the old addresses 204 * PM1A_EVT == 0x1f40; PM1A_CNT == 0x1f44; PM_TMR == 0x1f48 205 * - 1: use the new default qemu addresses 206 * PM1A_EVT == 0xb000; PM1A_CNT == 0xb004; PM_TMR == 0xb008 207 * You can find these address definitions in <hvm/ioreq.h> 208 */ 209 #define HVM_PARAM_ACPI_IOPORTS_LOCATION 19 210 211 /* Deprecated */ 212 #define HVM_PARAM_MEMORY_EVENT_CR0 20 213 #define HVM_PARAM_MEMORY_EVENT_CR3 21 214 #define HVM_PARAM_MEMORY_EVENT_CR4 22 215 #define HVM_PARAM_MEMORY_EVENT_INT3 23 216 #define HVM_PARAM_MEMORY_EVENT_SINGLE_STEP 25 217 #define HVM_PARAM_MEMORY_EVENT_MSR 30 218 219 /* Boolean: Enable nestedhvm (hvm only) */ 220 #define HVM_PARAM_NESTEDHVM 24 221 222 /* Params for the mem event rings */ 223 #define HVM_PARAM_PAGING_RING_PFN 27 224 #define HVM_PARAM_MONITOR_RING_PFN 28 225 #define HVM_PARAM_SHARING_RING_PFN 29 226 227 /* SHUTDOWN_* action in case of a triple fault */ 228 #define HVM_PARAM_TRIPLE_FAULT_REASON 31 229 230 #define HVM_PARAM_IOREQ_SERVER_PFN 32 231 #define HVM_PARAM_NR_IOREQ_SERVER_PAGES 33 232 233 /* Location of the VM Generation ID in guest physical address space. */ 234 #define HVM_PARAM_VM_GENERATION_ID_ADDR 34 235 236 /* 237 * Set mode for altp2m: 238 * disabled: don't activate altp2m (default) 239 * mixed: allow access to all altp2m ops for both in-guest and external tools 240 * external: allow access to external privileged tools only 241 * limited: guest only has limited access (ie. control VMFUNC and #VE) 242 */ 243 #define HVM_PARAM_ALTP2M 35 244 #define XEN_ALTP2M_disabled 0 245 #define XEN_ALTP2M_mixed 1 246 #define XEN_ALTP2M_external 2 247 #define XEN_ALTP2M_limited 3 248 249 /* 250 * Size of the x87 FPU FIP/FDP registers that the hypervisor needs to 251 * save/restore. This is a workaround for a hardware limitation that 252 * does not allow the full FIP/FDP and FCS/FDS to be restored. 253 * 254 * Valid values are: 255 * 256 * 8: save/restore 64-bit FIP/FDP and clear FCS/FDS (default if CPU 257 * has FPCSDS feature). 258 * 259 * 4: save/restore 32-bit FIP/FDP, FCS/FDS, and clear upper 32-bits of 260 * FIP/FDP. 261 * 262 * 0: allow hypervisor to choose based on the value of FIP/FDP 263 * (default if CPU does not have FPCSDS). 264 * 265 * If FPCSDS (bit 13 in CPUID leaf 0x7, subleaf 0x0) is set, the CPU 266 * never saves FCS/FDS and this parameter should be left at the 267 * default of 8. 268 */ 269 #define HVM_PARAM_X87_FIP_WIDTH 36 270 271 /* 272 * TSS (and its size) used on Intel when CR0.PE=0. The address occupies 273 * the low 32 bits, while the size is in the high 32 ones. 274 */ 275 #define HVM_PARAM_VM86_TSS_SIZED 37 276 277 /* Enable MCA capabilities. */ 278 #define HVM_PARAM_MCA_CAP 38 279 #define XEN_HVM_MCA_CAP_LMCE (xen_mk_ullong(1) << 0) 280 #define XEN_HVM_MCA_CAP_MASK XEN_HVM_MCA_CAP_LMCE 281 282 #define HVM_NR_PARAMS 39 283 284 #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */ 285