1 /* 2 * Copyright (C) 2007 Advanced Micro Devices, Inc. 3 * Author: Leo Duran <leo.duran@amd.com> 4 * Author: Wei Wang <wei.wang2@amd.com> - adapted to xen 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef _ASM_X86_64_AMD_IOMMU_DEFS_H 21 #define _ASM_X86_64_AMD_IOMMU_DEFS_H 22 23 /* IOMMU Command Buffer entries: in power of 2 increments, minimum of 256 */ 24 #define IOMMU_CMD_BUFFER_DEFAULT_ENTRIES 512 25 26 /* IOMMU Event Log entries: in power of 2 increments, minimum of 256 */ 27 #define IOMMU_EVENT_LOG_DEFAULT_ENTRIES 512 28 29 /* IOMMU PPR Log entries: in power of 2 increments, minimum of 256 */ 30 #define IOMMU_PPR_LOG_DEFAULT_ENTRIES 512 31 32 #define PTE_PER_TABLE_SHIFT 9 33 #define PTE_PER_TABLE_SIZE (1 << PTE_PER_TABLE_SHIFT) 34 #define PTE_PER_TABLE_MASK (~(PTE_PER_TABLE_SIZE - 1)) 35 #define PTE_PER_TABLE_ALIGN(entries) \ 36 (((entries) + PTE_PER_TABLE_SIZE - 1) & PTE_PER_TABLE_MASK) 37 #define PTE_PER_TABLE_ALLOC(entries) \ 38 PAGE_SIZE * (PTE_PER_TABLE_ALIGN(entries) >> PTE_PER_TABLE_SHIFT) 39 40 #define amd_offset_level_address(offset, level) \ 41 ((u64)(offset) << (12 + (PTE_PER_TABLE_SHIFT * \ 42 (level - IOMMU_PAGING_MODE_LEVEL_1)))) 43 44 #define PCI_MIN_CAP_OFFSET 0x40 45 #define PCI_MAX_CAP_BLOCKS 48 46 #define PCI_CAP_PTR_MASK 0xFC 47 48 /* IOMMU Capability */ 49 #define PCI_CAP_ID_MASK 0x000000FF 50 #define PCI_CAP_ID_SHIFT 0 51 #define PCI_CAP_NEXT_PTR_MASK 0x0000FF00 52 #define PCI_CAP_NEXT_PTR_SHIFT 8 53 #define PCI_CAP_TYPE_MASK 0x00070000 54 #define PCI_CAP_TYPE_SHIFT 16 55 #define PCI_CAP_REV_MASK 0x00F80000 56 #define PCI_CAP_REV_SHIFT 19 57 #define PCI_CAP_IOTLB_MASK 0x01000000 58 #define PCI_CAP_IOTLB_SHIFT 24 59 #define PCI_CAP_HT_TUNNEL_MASK 0x02000000 60 #define PCI_CAP_HT_TUNNEL_SHIFT 25 61 #define PCI_CAP_NP_CACHE_MASK 0x04000000 62 #define PCI_CAP_NP_CACHE_SHIFT 26 63 #define PCI_CAP_EFRSUP_SHIFT 27 64 #define PCI_CAP_RESET_MASK 0x80000000 65 #define PCI_CAP_RESET_SHIFT 31 66 67 #define PCI_CAP_TYPE_IOMMU 0x3 68 69 #define PCI_CAP_MMIO_BAR_LOW_OFFSET 0x04 70 #define PCI_CAP_MMIO_BAR_HIGH_OFFSET 0x08 71 #define PCI_CAP_MMIO_BAR_LOW_MASK 0xFFFFC000 72 #define IOMMU_MMIO_REGION_LENGTH 0x4000 73 74 #define PCI_CAP_RANGE_OFFSET 0x0C 75 #define PCI_CAP_BUS_NUMBER_MASK 0x0000FF00 76 #define PCI_CAP_BUS_NUMBER_SHIFT 8 77 #define PCI_CAP_FIRST_DEVICE_MASK 0x00FF0000 78 #define PCI_CAP_FIRST_DEVICE_SHIFT 16 79 #define PCI_CAP_LAST_DEVICE_MASK 0xFF000000 80 #define PCI_CAP_LAST_DEVICE_SHIFT 24 81 82 #define PCI_CAP_UNIT_ID_MASK 0x0000001F 83 #define PCI_CAP_UNIT_ID_SHIFT 0 84 #define PCI_CAP_MISC_INFO_OFFSET 0x10 85 #define PCI_CAP_MSI_NUMBER_MASK 0x0000001F 86 #define PCI_CAP_MSI_NUMBER_SHIFT 0 87 88 /* Device Table */ 89 #define IOMMU_DEV_TABLE_BASE_LOW_OFFSET 0x00 90 #define IOMMU_DEV_TABLE_BASE_HIGH_OFFSET 0x04 91 #define IOMMU_DEV_TABLE_SIZE_MASK 0x000001FF 92 #define IOMMU_DEV_TABLE_SIZE_SHIFT 0 93 94 #define IOMMU_DEV_TABLE_ENTRIES_PER_BUS 256 95 #define IOMMU_DEV_TABLE_ENTRY_SIZE 32 96 #define IOMMU_DEV_TABLE_U32_PER_ENTRY (IOMMU_DEV_TABLE_ENTRY_SIZE / 4) 97 98 #define IOMMU_DEV_TABLE_SYS_MGT_DMA_ABORTED 0x0 99 #define IOMMU_DEV_TABLE_SYS_MGT_MSG_FORWARDED 0x1 100 #define IOMMU_DEV_TABLE_SYS_MGT_INT_FORWARDED 0x2 101 #define IOMMU_DEV_TABLE_SYS_MGT_DMA_FORWARDED 0x3 102 103 #define IOMMU_DEV_TABLE_IO_CONTROL_ABORTED 0x0 104 #define IOMMU_DEV_TABLE_IO_CONTROL_FORWARDED 0x1 105 #define IOMMU_DEV_TABLE_IO_CONTROL_TRANSLATED 0x2 106 107 #define IOMMU_DEV_TABLE_INT_CONTROL_ABORTED 0x0 108 #define IOMMU_DEV_TABLE_INT_CONTROL_FORWARDED 0x1 109 #define IOMMU_DEV_TABLE_INT_CONTROL_TRANSLATED 0x2 110 111 /* DeviceTable Entry[31:0] */ 112 #define IOMMU_DEV_TABLE_VALID_MASK 0x00000001 113 #define IOMMU_DEV_TABLE_VALID_SHIFT 0 114 #define IOMMU_DEV_TABLE_TRANSLATION_VALID_MASK 0x00000002 115 #define IOMMU_DEV_TABLE_TRANSLATION_VALID_SHIFT 1 116 #define IOMMU_DEV_TABLE_PAGING_MODE_MASK 0x00000E00 117 #define IOMMU_DEV_TABLE_PAGING_MODE_SHIFT 9 118 #define IOMMU_DEV_TABLE_PAGE_TABLE_PTR_LOW_MASK 0xFFFFF000 119 #define IOMMU_DEV_TABLE_PAGE_TABLE_PTR_LOW_SHIFT 12 120 121 /* DeviceTable Entry[63:32] */ 122 #define IOMMU_DEV_TABLE_GV_SHIFT 23 123 #define IOMMU_DEV_TABLE_GV_MASK 0x800000 124 #define IOMMU_DEV_TABLE_GLX_SHIFT 24 125 #define IOMMU_DEV_TABLE_GLX_MASK 0x3000000 126 #define IOMMU_DEV_TABLE_GCR3_1_SHIFT 26 127 #define IOMMU_DEV_TABLE_GCR3_1_MASK 0x1c000000 128 129 #define IOMMU_DEV_TABLE_PAGE_TABLE_PTR_HIGH_MASK 0x000FFFFF 130 #define IOMMU_DEV_TABLE_PAGE_TABLE_PTR_HIGH_SHIFT 0 131 #define IOMMU_DEV_TABLE_IO_READ_PERMISSION_MASK 0x20000000 132 #define IOMMU_DEV_TABLE_IO_READ_PERMISSION_SHIFT 29 133 #define IOMMU_DEV_TABLE_IO_WRITE_PERMISSION_MASK 0x40000000 134 #define IOMMU_DEV_TABLE_IO_WRITE_PERMISSION_SHIFT 30 135 136 /* DeviceTable Entry[95:64] */ 137 #define IOMMU_DEV_TABLE_DOMAIN_ID_MASK 0x0000FFFF 138 #define IOMMU_DEV_TABLE_DOMAIN_ID_SHIFT 0 139 #define IOMMU_DEV_TABLE_GCR3_2_SHIFT 16 140 #define IOMMU_DEV_TABLE_GCR3_2_MASK 0xFFFF0000 141 142 /* DeviceTable Entry[127:96] */ 143 #define IOMMU_DEV_TABLE_IOTLB_SUPPORT_MASK 0x00000001 144 #define IOMMU_DEV_TABLE_IOTLB_SUPPORT_SHIFT 0 145 #define IOMMU_DEV_TABLE_SUPRESS_LOGGED_PAGES_MASK 0x00000002 146 #define IOMMU_DEV_TABLE_SUPRESS_LOGGED_PAGES_SHIFT 1 147 #define IOMMU_DEV_TABLE_SUPRESS_ALL_PAGES_MASK 0x00000004 148 #define IOMMU_DEV_TABLE_SUPRESS_ALL_PAGES_SHIFT 2 149 #define IOMMU_DEV_TABLE_IO_CONTROL_MASK 0x00000018 150 #define IOMMU_DEV_TABLE_IO_CONTROL_SHIFT 3 151 #define IOMMU_DEV_TABLE_IOTLB_CACHE_HINT_MASK 0x00000020 152 #define IOMMU_DEV_TABLE_IOTLB_CACHE_HINT_SHIFT 5 153 #define IOMMU_DEV_TABLE_SNOOP_DISABLE_MASK 0x00000040 154 #define IOMMU_DEV_TABLE_SNOOP_DISABLE_SHIFT 6 155 #define IOMMU_DEV_TABLE_ALLOW_EXCLUSION_MASK 0x00000080 156 #define IOMMU_DEV_TABLE_ALLOW_EXCLUSION_SHIFT 7 157 #define IOMMU_DEV_TABLE_SYS_MGT_MSG_ENABLE_MASK 0x00000300 158 #define IOMMU_DEV_TABLE_SYS_MGT_MSG_ENABLE_SHIFT 8 159 160 /* DeviceTable Entry[159:128] */ 161 #define IOMMU_DEV_TABLE_INT_VALID_MASK 0x00000001 162 #define IOMMU_DEV_TABLE_INT_VALID_SHIFT 0 163 #define IOMMU_DEV_TABLE_INT_TABLE_LENGTH_MASK 0x0000001E 164 #define IOMMU_DEV_TABLE_INT_TABLE_LENGTH_SHIFT 1 165 #define IOMMU_DEV_TABLE_INT_TABLE_IGN_UNMAPPED_MASK 0x0000000020 166 #define IOMMU_DEV_TABLE_INT_TABLE_IGN_UNMAPPED_SHIFT 5 167 #define IOMMU_DEV_TABLE_INT_TABLE_PTR_LOW_MASK 0xFFFFFFC0 168 #define IOMMU_DEV_TABLE_INT_TABLE_PTR_LOW_SHIFT 6 169 #define IOMMU_DEV_TABLE_GCR3_3_SHIFT 11 170 #define IOMMU_DEV_TABLE_GCR3_3_MASK 0xfffff800 171 172 /* DeviceTable Entry[191:160] */ 173 #define IOMMU_DEV_TABLE_INT_TABLE_PTR_HIGH_MASK 0x000FFFFF 174 #define IOMMU_DEV_TABLE_INT_TABLE_PTR_HIGH_SHIFT 0 175 #define IOMMU_DEV_TABLE_IVHD_FLAGS_SHIFT 24 176 #define IOMMU_DEV_TABLE_IVHD_FLAGS_MASK 0xC7000000 177 #define IOMMU_DEV_TABLE_INT_CONTROL_MASK 0x30000000 178 #define IOMMU_DEV_TABLE_INT_CONTROL_SHIFT 28 179 180 /* Command Buffer */ 181 #define IOMMU_CMD_BUFFER_BASE_LOW_OFFSET 0x08 182 #define IOMMU_CMD_BUFFER_BASE_HIGH_OFFSET 0x0C 183 #define IOMMU_CMD_BUFFER_HEAD_OFFSET 0x2000 184 #define IOMMU_CMD_BUFFER_TAIL_OFFSET 0x2008 185 #define IOMMU_CMD_BUFFER_LENGTH_MASK 0x0F000000 186 #define IOMMU_CMD_BUFFER_LENGTH_SHIFT 24 187 188 #define IOMMU_CMD_BUFFER_ENTRY_SIZE 16 189 #define IOMMU_CMD_BUFFER_POWER_OF2_ENTRIES_PER_PAGE 8 190 #define IOMMU_CMD_BUFFER_U32_PER_ENTRY (IOMMU_CMD_BUFFER_ENTRY_SIZE / 4) 191 192 #define IOMMU_CMD_OPCODE_MASK 0xF0000000 193 #define IOMMU_CMD_OPCODE_SHIFT 28 194 #define IOMMU_CMD_COMPLETION_WAIT 0x1 195 #define IOMMU_CMD_INVALIDATE_DEVTAB_ENTRY 0x2 196 #define IOMMU_CMD_INVALIDATE_IOMMU_PAGES 0x3 197 #define IOMMU_CMD_INVALIDATE_IOTLB_PAGES 0x4 198 #define IOMMU_CMD_INVALIDATE_INT_TABLE 0x5 199 #define IOMMU_CMD_COMPLETE_PPR_REQUEST 0x7 200 #define IOMMU_CMD_INVALIDATE_IOMMU_ALL 0x8 201 202 /* COMPLETION_WAIT command */ 203 #define IOMMU_COMP_WAIT_DATA_BUFFER_SIZE 8 204 #define IOMMU_COMP_WAIT_DATA_BUFFER_ALIGNMENT 8 205 #define IOMMU_COMP_WAIT_S_FLAG_MASK 0x00000001 206 #define IOMMU_COMP_WAIT_S_FLAG_SHIFT 0 207 #define IOMMU_COMP_WAIT_I_FLAG_MASK 0x00000002 208 #define IOMMU_COMP_WAIT_I_FLAG_SHIFT 1 209 #define IOMMU_COMP_WAIT_F_FLAG_MASK 0x00000004 210 #define IOMMU_COMP_WAIT_F_FLAG_SHIFT 2 211 #define IOMMU_COMP_WAIT_ADDR_LOW_MASK 0xFFFFFFF8 212 #define IOMMU_COMP_WAIT_ADDR_LOW_SHIFT 3 213 #define IOMMU_COMP_WAIT_ADDR_HIGH_MASK 0x000FFFFF 214 #define IOMMU_COMP_WAIT_ADDR_HIGH_SHIFT 0 215 216 /* INVALIDATE_IOMMU_PAGES command */ 217 #define IOMMU_INV_IOMMU_PAGES_DOMAIN_ID_MASK 0x0000FFFF 218 #define IOMMU_INV_IOMMU_PAGES_DOMAIN_ID_SHIFT 0 219 #define IOMMU_INV_IOMMU_PAGES_S_FLAG_MASK 0x00000001 220 #define IOMMU_INV_IOMMU_PAGES_S_FLAG_SHIFT 0 221 #define IOMMU_INV_IOMMU_PAGES_PDE_FLAG_MASK 0x00000002 222 #define IOMMU_INV_IOMMU_PAGES_PDE_FLAG_SHIFT 1 223 #define IOMMU_INV_IOMMU_PAGES_ADDR_LOW_MASK 0xFFFFF000 224 #define IOMMU_INV_IOMMU_PAGES_ADDR_LOW_SHIFT 12 225 #define IOMMU_INV_IOMMU_PAGES_ADDR_HIGH_MASK 0xFFFFFFFF 226 #define IOMMU_INV_IOMMU_PAGES_ADDR_HIGH_SHIFT 0 227 228 /* INVALIDATE_DEVTAB_ENTRY command */ 229 #define IOMMU_INV_DEVTAB_ENTRY_DEVICE_ID_MASK 0x0000FFFF 230 #define IOMMU_INV_DEVTAB_ENTRY_DEVICE_ID_SHIFT 0 231 232 /* INVALIDATE_INTERRUPT_TABLE command */ 233 #define IOMMU_INV_INT_TABLE_DEVICE_ID_MASK 0x0000FFFF 234 #define IOMMU_INV_INT_TABLE_DEVICE_ID_SHIFT 0 235 236 /* INVALIDATE_IOTLB_PAGES command */ 237 #define IOMMU_INV_IOTLB_PAGES_MAXPEND_MASK 0xff000000 238 #define IOMMU_INV_IOTLB_PAGES_MAXPEND_SHIFT 24 239 #define IOMMU_INV_IOTLB_PAGES_PASID1_MASK 0x00ff0000 240 #define IOMMU_INV_IOTLB_PAGES_PASID1_SHIFT 16 241 #define IOMMU_INV_IOTLB_PAGES_PASID2_MASK 0x0fff0000 242 #define IOMMU_INV_IOTLB_PAGES_PASID2_SHIFT 16 243 #define IOMMU_INV_IOTLB_PAGES_QUEUEID_MASK 0x0000ffff 244 #define IOMMU_INV_IOTLB_PAGES_QUEUEID_SHIFT 0 245 #define IOMMU_INV_IOTLB_PAGES_DEVICE_ID_MASK 0x0000FFFF 246 #define IOMMU_INV_IOTLB_PAGES_DEVICE_ID_SHIFT 0 247 #define IOMMU_INV_IOTLB_PAGES_ADDR_LOW_MASK 0xFFFFF000 248 #define IOMMU_INV_IOTLB_PAGES_ADDR_LOW_SHIFT 12 249 #define IOMMU_INV_IOTLB_PAGES_ADDR_HIGH_MASK 0xFFFFFFFF 250 #define IOMMU_INV_IOTLB_PAGES_ADDR_HIGH_SHIFT 0 251 #define IOMMU_INV_IOTLB_PAGES_S_FLAG_MASK 0x00000001 252 #define IOMMU_INV_IOTLB_PAGES_S_FLAG_SHIFT 0 253 254 /* Event Log */ 255 #define IOMMU_EVENT_LOG_BASE_LOW_OFFSET 0x10 256 #define IOMMU_EVENT_LOG_BASE_HIGH_OFFSET 0x14 257 #define IOMMU_EVENT_LOG_HEAD_OFFSET 0x2010 258 #define IOMMU_EVENT_LOG_TAIL_OFFSET 0x2018 259 #define IOMMU_EVENT_LOG_LENGTH_MASK 0x0F000000 260 #define IOMMU_EVENT_LOG_LENGTH_SHIFT 24 261 #define IOMMU_EVENT_LOG_HEAD_MASK 0x0007FFF0 262 #define IOMMU_EVENT_LOG_HEAD_SHIFT 4 263 #define IOMMU_EVENT_LOG_TAIL_MASK 0x0007FFF0 264 #define IOMMU_EVENT_LOG_TAIL_SHIFT 4 265 266 #define IOMMU_EVENT_LOG_ENTRY_SIZE 16 267 #define IOMMU_EVENT_LOG_POWER_OF2_ENTRIES_PER_PAGE 8 268 #define IOMMU_EVENT_LOG_U32_PER_ENTRY (IOMMU_EVENT_LOG_ENTRY_SIZE / 4) 269 270 #define IOMMU_EVENT_CODE_MASK 0xF0000000 271 #define IOMMU_EVENT_CODE_SHIFT 28 272 #define IOMMU_EVENT_ILLEGAL_DEV_TABLE_ENTRY 0x1 273 #define IOMMU_EVENT_IO_PAGE_FAULT 0x2 274 #define IOMMU_EVENT_DEV_TABLE_HW_ERROR 0x3 275 #define IOMMU_EVENT_PAGE_TABLE_HW_ERROR 0x4 276 #define IOMMU_EVENT_ILLEGAL_COMMAND_ERROR 0x5 277 #define IOMMU_EVENT_COMMAND_HW_ERROR 0x6 278 #define IOMMU_EVENT_IOTLB_INV_TIMEOUT 0x7 279 #define IOMMU_EVENT_INVALID_DEV_REQUEST 0x8 280 281 #define IOMMU_EVENT_DOMAIN_ID_MASK 0x0000FFFF 282 #define IOMMU_EVENT_DOMAIN_ID_SHIFT 0 283 #define IOMMU_EVENT_DEVICE_ID_MASK 0x0000FFFF 284 #define IOMMU_EVENT_DEVICE_ID_SHIFT 0 285 #define IOMMU_EVENT_FLAGS_SHIFT 16 286 #define IOMMU_EVENT_FLAGS_MASK 0x0FFF0000 287 288 /* PPR Log */ 289 #define IOMMU_PPR_LOG_ENTRY_SIZE 16 290 #define IOMMU_PPR_LOG_POWER_OF2_ENTRIES_PER_PAGE 8 291 #define IOMMU_PPR_LOG_U32_PER_ENTRY (IOMMU_PPR_LOG_ENTRY_SIZE / 4) 292 293 #define IOMMU_PPR_LOG_BASE_LOW_OFFSET 0x0038 294 #define IOMMU_PPR_LOG_BASE_HIGH_OFFSET 0x003C 295 #define IOMMU_PPR_LOG_BASE_LOW_MASK 0xFFFFF000 296 #define IOMMU_PPR_LOG_BASE_LOW_SHIFT 12 297 #define IOMMU_PPR_LOG_BASE_HIGH_MASK 0x000FFFFF 298 #define IOMMU_PPR_LOG_BASE_HIGH_SHIFT 0 299 #define IOMMU_PPR_LOG_LENGTH_MASK 0x0F000000 300 #define IOMMU_PPR_LOG_LENGTH_SHIFT 24 301 #define IOMMU_PPR_LOG_HEAD_MASK 0x0007FFF0 302 #define IOMMU_PPR_LOG_HEAD_SHIFT 4 303 #define IOMMU_PPR_LOG_TAIL_MASK 0x0007FFF0 304 #define IOMMU_PPR_LOG_TAIL_SHIFT 4 305 #define IOMMU_PPR_LOG_HEAD_OFFSET 0x2030 306 #define IOMMU_PPR_LOG_TAIL_OFFSET 0x2038 307 #define IOMMU_PPR_LOG_DEVICE_ID_MASK 0x0000FFFF 308 #define IOMMU_PPR_LOG_DEVICE_ID_SHIFT 0 309 #define IOMMU_PPR_LOG_CODE_MASK 0xF0000000 310 #define IOMMU_PPR_LOG_CODE_SHIFT 28 311 312 #define IOMMU_LOG_ENTRY_TIMEOUT 1000 313 314 /* Control Register */ 315 #define IOMMU_CONTROL_MMIO_OFFSET 0x18 316 #define IOMMU_CONTROL_TRANSLATION_ENABLE_MASK 0x00000001 317 #define IOMMU_CONTROL_TRANSLATION_ENABLE_SHIFT 0 318 #define IOMMU_CONTROL_HT_TUNNEL_TRANSLATION_MASK 0x00000002 319 #define IOMMU_CONTROL_HT_TUNNEL_TRANSLATION_SHIFT 1 320 #define IOMMU_CONTROL_EVENT_LOG_ENABLE_MASK 0x00000004 321 #define IOMMU_CONTROL_EVENT_LOG_ENABLE_SHIFT 2 322 #define IOMMU_CONTROL_EVENT_LOG_INT_MASK 0x00000008 323 #define IOMMU_CONTROL_EVENT_LOG_INT_SHIFT 3 324 #define IOMMU_CONTROL_COMP_WAIT_INT_MASK 0x00000010 325 #define IOMMU_CONTROL_COMP_WAIT_INT_SHIFT 4 326 #define IOMMU_CONTROL_INVALIDATION_TIMEOUT_MASK 0x000000E0 327 #define IOMMU_CONTROL_INVALIDATION_TIMEOUT_SHIFT 5 328 #define IOMMU_CONTROL_PASS_POSTED_WRITE_MASK 0x00000100 329 #define IOMMU_CONTROL_PASS_POSTED_WRITE_SHIFT 8 330 #define IOMMU_CONTROL_RESP_PASS_POSTED_WRITE_MASK 0x00000200 331 #define IOMMU_CONTROL_RESP_PASS_POSTED_WRITE_SHIFT 9 332 #define IOMMU_CONTROL_COHERENT_MASK 0x00000400 333 #define IOMMU_CONTROL_COHERENT_SHIFT 10 334 #define IOMMU_CONTROL_ISOCHRONOUS_MASK 0x00000800 335 #define IOMMU_CONTROL_ISOCHRONOUS_SHIFT 11 336 #define IOMMU_CONTROL_COMMAND_BUFFER_ENABLE_MASK 0x00001000 337 #define IOMMU_CONTROL_COMMAND_BUFFER_ENABLE_SHIFT 12 338 #define IOMMU_CONTROL_PPR_LOG_ENABLE_MASK 0x00002000 339 #define IOMMU_CONTROL_PPR_LOG_ENABLE_SHIFT 13 340 #define IOMMU_CONTROL_PPR_LOG_INT_MASK 0x00004000 341 #define IOMMU_CONTROL_PPR_LOG_INT_SHIFT 14 342 #define IOMMU_CONTROL_PPR_ENABLE_MASK 0x00008000 343 #define IOMMU_CONTROL_PPR_ENABLE_SHIFT 15 344 #define IOMMU_CONTROL_GT_ENABLE_MASK 0x00010000 345 #define IOMMU_CONTROL_GT_ENABLE_SHIFT 16 346 #define IOMMU_CONTROL_RESTART_MASK 0x80000000 347 #define IOMMU_CONTROL_RESTART_SHIFT 31 348 349 /* Exclusion Register */ 350 #define IOMMU_EXCLUSION_BASE_LOW_OFFSET 0x20 351 #define IOMMU_EXCLUSION_BASE_HIGH_OFFSET 0x24 352 #define IOMMU_EXCLUSION_LIMIT_LOW_OFFSET 0x28 353 #define IOMMU_EXCLUSION_LIMIT_HIGH_OFFSET 0x2C 354 #define IOMMU_EXCLUSION_BASE_LOW_MASK 0xFFFFF000 355 #define IOMMU_EXCLUSION_BASE_LOW_SHIFT 12 356 #define IOMMU_EXCLUSION_BASE_HIGH_MASK 0xFFFFFFFF 357 #define IOMMU_EXCLUSION_BASE_HIGH_SHIFT 0 358 #define IOMMU_EXCLUSION_RANGE_ENABLE_MASK 0x00000001 359 #define IOMMU_EXCLUSION_RANGE_ENABLE_SHIFT 0 360 #define IOMMU_EXCLUSION_ALLOW_ALL_MASK 0x00000002 361 #define IOMMU_EXCLUSION_ALLOW_ALL_SHIFT 1 362 #define IOMMU_EXCLUSION_LIMIT_LOW_MASK 0xFFFFF000 363 #define IOMMU_EXCLUSION_LIMIT_LOW_SHIFT 12 364 #define IOMMU_EXCLUSION_LIMIT_HIGH_MASK 0xFFFFFFFF 365 #define IOMMU_EXCLUSION_LIMIT_HIGH_SHIFT 0 366 367 /* Extended Feature Register*/ 368 #define IOMMU_EXT_FEATURE_MMIO_OFFSET 0x30 369 #define IOMMU_EXT_FEATURE_PREFSUP_SHIFT 0x0 370 #define IOMMU_EXT_FEATURE_PPRSUP_SHIFT 0x1 371 #define IOMMU_EXT_FEATURE_XTSUP_SHIFT 0x2 372 #define IOMMU_EXT_FEATURE_NXSUP_SHIFT 0x3 373 #define IOMMU_EXT_FEATURE_GTSUP_SHIFT 0x4 374 #define IOMMU_EXT_FEATURE_IASUP_SHIFT 0x6 375 #define IOMMU_EXT_FEATURE_GASUP_SHIFT 0x7 376 #define IOMMU_EXT_FEATURE_HESUP_SHIFT 0x8 377 #define IOMMU_EXT_FEATURE_PCSUP_SHIFT 0x9 378 #define IOMMU_EXT_FEATURE_HATS_SHIFT 0x10 379 #define IOMMU_EXT_FEATURE_HATS_MASK 0x00000C00 380 #define IOMMU_EXT_FEATURE_GATS_SHIFT 0x12 381 #define IOMMU_EXT_FEATURE_GATS_MASK 0x00003000 382 #define IOMMU_EXT_FEATURE_GLXSUP_SHIFT 0x14 383 #define IOMMU_EXT_FEATURE_GLXSUP_MASK 0x0000C000 384 385 #define IOMMU_EXT_FEATURE_PASMAX_SHIFT 0x0 386 #define IOMMU_EXT_FEATURE_PASMAX_MASK 0x0000001F 387 388 /* Status Register*/ 389 #define IOMMU_STATUS_MMIO_OFFSET 0x2020 390 #define IOMMU_STATUS_EVENT_OVERFLOW_MASK 0x00000001 391 #define IOMMU_STATUS_EVENT_OVERFLOW_SHIFT 0 392 #define IOMMU_STATUS_EVENT_LOG_INT_MASK 0x00000002 393 #define IOMMU_STATUS_EVENT_LOG_INT_SHIFT 1 394 #define IOMMU_STATUS_COMP_WAIT_INT_MASK 0x00000004 395 #define IOMMU_STATUS_COMP_WAIT_INT_SHIFT 2 396 #define IOMMU_STATUS_EVENT_LOG_RUN_MASK 0x00000008 397 #define IOMMU_STATUS_EVENT_LOG_RUN_SHIFT 3 398 #define IOMMU_STATUS_CMD_BUFFER_RUN_MASK 0x00000010 399 #define IOMMU_STATUS_CMD_BUFFER_RUN_SHIFT 4 400 #define IOMMU_STATUS_PPR_LOG_OVERFLOW_MASK 0x00000020 401 #define IOMMU_STATUS_PPR_LOG_OVERFLOW_SHIFT 5 402 #define IOMMU_STATUS_PPR_LOG_INT_MASK 0x00000040 403 #define IOMMU_STATUS_PPR_LOG_INT_SHIFT 6 404 #define IOMMU_STATUS_PPR_LOG_RUN_MASK 0x00000080 405 #define IOMMU_STATUS_PPR_LOG_RUN_SHIFT 7 406 #define IOMMU_STATUS_GAPIC_LOG_OVERFLOW_MASK 0x00000100 407 #define IOMMU_STATUS_GAPIC_LOG_OVERFLOW_SHIFT 8 408 #define IOMMU_STATUS_GAPIC_LOG_INT_MASK 0x00000200 409 #define IOMMU_STATUS_GAPIC_LOG_INT_SHIFT 9 410 #define IOMMU_STATUS_GAPIC_LOG_RUN_MASK 0x00000400 411 #define IOMMU_STATUS_GAPIC_LOG_RUN_SHIFT 10 412 413 /* I/O Page Table */ 414 #define IOMMU_PAGE_TABLE_ENTRY_SIZE 8 415 #define IOMMU_PAGE_TABLE_U32_PER_ENTRY (IOMMU_PAGE_TABLE_ENTRY_SIZE / 4) 416 #define IOMMU_PAGE_TABLE_ALIGNMENT 4096 417 418 #define IOMMU_PTE_PRESENT_MASK 0x00000001 419 #define IOMMU_PTE_PRESENT_SHIFT 0 420 #define IOMMU_PTE_NEXT_LEVEL_MASK 0x00000E00 421 #define IOMMU_PTE_NEXT_LEVEL_SHIFT 9 422 #define IOMMU_PTE_ADDR_LOW_MASK 0xFFFFF000 423 #define IOMMU_PTE_ADDR_LOW_SHIFT 12 424 #define IOMMU_PTE_ADDR_HIGH_MASK 0x000FFFFF 425 #define IOMMU_PTE_ADDR_HIGH_SHIFT 0 426 #define IOMMU_PTE_U_MASK 0x08000000 427 #define IOMMU_PTE_U_SHIFT 7 428 #define IOMMU_PTE_FC_MASK 0x10000000 429 #define IOMMU_PTE_FC_SHIFT 28 430 #define IOMMU_PTE_IO_READ_PERMISSION_MASK 0x20000000 431 #define IOMMU_PTE_IO_READ_PERMISSION_SHIFT 29 432 #define IOMMU_PTE_IO_WRITE_PERMISSION_MASK 0x40000000 433 #define IOMMU_PTE_IO_WRITE_PERMISSION_SHIFT 30 434 435 /* I/O Page Directory */ 436 #define IOMMU_PAGE_DIRECTORY_ENTRY_SIZE 8 437 #define IOMMU_PAGE_DIRECTORY_ALIGNMENT 4096 438 #define IOMMU_PDE_PRESENT_MASK 0x00000001 439 #define IOMMU_PDE_PRESENT_SHIFT 0 440 #define IOMMU_PDE_NEXT_LEVEL_MASK 0x00000E00 441 #define IOMMU_PDE_NEXT_LEVEL_SHIFT 9 442 #define IOMMU_PDE_ADDR_LOW_MASK 0xFFFFF000 443 #define IOMMU_PDE_ADDR_LOW_SHIFT 12 444 #define IOMMU_PDE_ADDR_HIGH_MASK 0x000FFFFF 445 #define IOMMU_PDE_ADDR_HIGH_SHIFT 0 446 #define IOMMU_PDE_IO_READ_PERMISSION_MASK 0x20000000 447 #define IOMMU_PDE_IO_READ_PERMISSION_SHIFT 29 448 #define IOMMU_PDE_IO_WRITE_PERMISSION_MASK 0x40000000 449 #define IOMMU_PDE_IO_WRITE_PERMISSION_SHIFT 30 450 451 /* Paging modes */ 452 #define IOMMU_PAGING_MODE_DISABLED 0x0 453 #define IOMMU_PAGING_MODE_LEVEL_0 0x0 454 #define IOMMU_PAGING_MODE_LEVEL_1 0x1 455 #define IOMMU_PAGING_MODE_LEVEL_2 0x2 456 #define IOMMU_PAGING_MODE_LEVEL_3 0x3 457 #define IOMMU_PAGING_MODE_LEVEL_4 0x4 458 #define IOMMU_PAGING_MODE_LEVEL_5 0x5 459 #define IOMMU_PAGING_MODE_LEVEL_6 0x6 460 #define IOMMU_PAGING_MODE_LEVEL_7 0x7 461 462 /* Flags */ 463 #define IOMMU_CONTROL_DISABLED 0 464 #define IOMMU_CONTROL_ENABLED 1 465 466 /* interrupt remapping table */ 467 #define INT_REMAP_ENTRY_REMAPEN_MASK 0x00000001 468 #define INT_REMAP_ENTRY_REMAPEN_SHIFT 0 469 #define INT_REMAP_ENTRY_SUPIOPF_MASK 0x00000002 470 #define INT_REMAP_ENTRY_SUPIOPF_SHIFT 1 471 #define INT_REMAP_ENTRY_INTTYPE_MASK 0x0000001C 472 #define INT_REMAP_ENTRY_INTTYPE_SHIFT 2 473 #define INT_REMAP_ENTRY_REQEOI_MASK 0x00000020 474 #define INT_REMAP_ENTRY_REQEOI_SHIFT 5 475 #define INT_REMAP_ENTRY_DM_MASK 0x00000040 476 #define INT_REMAP_ENTRY_DM_SHIFT 6 477 #define INT_REMAP_ENTRY_DEST_MAST 0x0000FF00 478 #define INT_REMAP_ENTRY_DEST_SHIFT 8 479 #define INT_REMAP_ENTRY_VECTOR_MASK 0x00FF0000 480 #define INT_REMAP_ENTRY_VECTOR_SHIFT 16 481 482 #define INV_IOMMU_ALL_PAGES_ADDRESS ((1ULL << 63) - 1) 483 484 #define IOMMU_RING_BUFFER_PTR_MASK 0x0007FFF0 485 #define IOMMU_RING_BUFFER_PTR_SHIFT 4 486 487 #define IOMMU_CMD_DEVICE_ID_MASK 0x0000FFFF 488 #define IOMMU_CMD_DEVICE_ID_SHIFT 0 489 490 #define IOMMU_CMD_ADDR_LOW_MASK 0xFFFFF000 491 #define IOMMU_CMD_ADDR_LOW_SHIFT 12 492 #define IOMMU_CMD_ADDR_HIGH_MASK 0xFFFFFFFF 493 #define IOMMU_CMD_ADDR_HIGH_SHIFT 0 494 495 #define IOMMU_REG_BASE_ADDR_LOW_MASK 0xFFFFF000 496 #define IOMMU_REG_BASE_ADDR_LOW_SHIFT 12 497 #define IOMMU_REG_BASE_ADDR_HIGH_MASK 0x000FFFFF 498 #define IOMMU_REG_BASE_ADDR_HIGH_SHIFT 0 499 500 #endif /* _ASM_X86_64_AMD_IOMMU_DEFS_H */ 501