Searched refs:LVL_1_DATA (Results 1 – 1 of 1) sorted by relevance
| /xen-4.10.0-shim-comet/xen/arch/x86/cpu/ |
| A D | intel_cacheinfo.c | 16 #define LVL_1_DATA 2 macro
33 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
34 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
39 { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
59 { 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
60 { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
61 { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
62 { 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
215 case LVL_1_DATA: in init_intel_cacheinfo()
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