Searched refs:LVL_3 (Results 1 – 1 of 1) sorted by relevance
| /xen-4.10.0-shim-comet/xen/arch/x86/cpu/ |
| A D | intel_cacheinfo.c | 18 #define LVL_3 4 macro
35 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
36 { 0x23, LVL_3, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */
52 { 0x46, LVL_3, 4096 }, /* 4-way set assoc, 64 byte line size */
53 { 0x47, LVL_3, 8192 }, /* 8-way set assoc, 64 byte line size */
54 { 0x49, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
55 { 0x4a, LVL_3, 6144 }, /* 12-way set assoc, 64 byte line size */
56 { 0x4b, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
57 { 0x4c, LVL_3, 12288 }, /* 12-way set assoc, 64 byte line size */
58 { 0x4d, LVL_3, 16384 }, /* 16-way set assoc, 64 byte line size */
[all …]
|
Completed in 2 milliseconds