Searched refs:MSR_AMD64_DR1_ADDRESS_MASK (Results 1 – 5 of 5) sorted by relevance
180 svm_intercept_msr(v, MSR_AMD64_DR1_ADDRESS_MASK, MSR_INTERCEPT_RW); in svm_save_dr()185 rdmsrl(MSR_AMD64_DR1_ADDRESS_MASK, v->arch.hvm_svm.dr_mask[1]); in svm_save_dr()211 svm_intercept_msr(v, MSR_AMD64_DR1_ADDRESS_MASK, MSR_INTERCEPT_NONE); in __restore_debug_registers()216 wrmsrl(MSR_AMD64_DR1_ADDRESS_MASK, v->arch.hvm_svm.dr_mask[1]); in __restore_debug_registers()412 ctxt->msr[ctxt->count++].index = MSR_AMD64_DR1_ADDRESS_MASK; in svm_save_msr()442 case MSR_AMD64_DR1_ADDRESS_MASK ... MSR_AMD64_DR3_ADDRESS_MASK: in svm_load_msr()448 v->arch.hvm_svm.dr_mask[idx - MSR_AMD64_DR1_ADDRESS_MASK + 1] = in svm_load_msr()1918 case MSR_AMD64_DR1_ADDRESS_MASK ... MSR_AMD64_DR3_ADDRESS_MASK: in svm_msr_read_intercept()1922 v->arch.hvm_svm.dr_mask[msr - MSR_AMD64_DR1_ADDRESS_MASK + 1]; in svm_msr_read_intercept()2074 case MSR_AMD64_DR1_ADDRESS_MASK ... MSR_AMD64_DR3_ADDRESS_MASK: in svm_msr_write_intercept()[all …]
942 case MSR_AMD64_DR1_ADDRESS_MASK ... MSR_AMD64_DR3_ADDRESS_MASK: in read_msr()945 *val = curr->arch.pv_vcpu.dr_mask[reg - MSR_AMD64_DR1_ADDRESS_MASK + 1]; in read_msr()1142 case MSR_AMD64_DR1_ADDRESS_MASK ... MSR_AMD64_DR3_ADDRESS_MASK: in write_msr()1145 curr->arch.pv_vcpu.dr_mask[reg - MSR_AMD64_DR1_ADDRESS_MASK + 1] = val; in write_msr()
212 #define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019 macro
1381 msr.index = MSR_AMD64_DR1_ADDRESS_MASK + j; in arch_do_domctl()1430 case MSR_AMD64_DR1_ADDRESS_MASK ... in arch_do_domctl()1435 msr.index -= MSR_AMD64_DR1_ADDRESS_MASK - 1; in arch_do_domctl()
1971 wrmsrl(MSR_AMD64_DR1_ADDRESS_MASK, curr->arch.pv_vcpu.dr_mask[1]); in activate_debugregs()
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