Searched refs:MSR_AMD64_DR3_ADDRESS_MASK (Results 1 – 5 of 5) sorted by relevance
182 svm_intercept_msr(v, MSR_AMD64_DR3_ADDRESS_MASK, MSR_INTERCEPT_RW); in svm_save_dr()187 rdmsrl(MSR_AMD64_DR3_ADDRESS_MASK, v->arch.hvm_svm.dr_mask[3]); in svm_save_dr()213 svm_intercept_msr(v, MSR_AMD64_DR3_ADDRESS_MASK, MSR_INTERCEPT_NONE); in __restore_debug_registers()218 wrmsrl(MSR_AMD64_DR3_ADDRESS_MASK, v->arch.hvm_svm.dr_mask[3]); in __restore_debug_registers()420 ctxt->msr[ctxt->count++].index = MSR_AMD64_DR3_ADDRESS_MASK; in svm_save_msr()442 case MSR_AMD64_DR1_ADDRESS_MASK ... MSR_AMD64_DR3_ADDRESS_MASK: in svm_load_msr()1918 case MSR_AMD64_DR1_ADDRESS_MASK ... MSR_AMD64_DR3_ADDRESS_MASK: in svm_msr_read_intercept()2074 case MSR_AMD64_DR1_ADDRESS_MASK ... MSR_AMD64_DR3_ADDRESS_MASK: in svm_msr_write_intercept()
214 #define MSR_AMD64_DR3_ADDRESS_MASK 0xc001101b macro
942 case MSR_AMD64_DR1_ADDRESS_MASK ... MSR_AMD64_DR3_ADDRESS_MASK: in read_msr()1142 case MSR_AMD64_DR1_ADDRESS_MASK ... MSR_AMD64_DR3_ADDRESS_MASK: in write_msr()
1973 wrmsrl(MSR_AMD64_DR3_ADDRESS_MASK, curr->arch.pv_vcpu.dr_mask[3]); in activate_debugregs()
1431 MSR_AMD64_DR3_ADDRESS_MASK: in arch_do_domctl()
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