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Searched refs:MSR_F10_MC4_MISC1 (Results 1 – 5 of 5) sorted by relevance

/xen-4.10.0-shim-comet/xen/arch/x86/cpu/mcheck/
A Dmce_amd.c232 mc_ext->mc_msr[0].reg = MSR_F10_MC4_MISC1; in amd_f10_handler()
236 mc_ext->mc_msr[0].value = mca_rdmsr(MSR_F10_MC4_MISC1); in amd_f10_handler()
A Dmce.h173 case MSR_F10_MC4_MISC1: in mce_vendor_bank_msr()
A Dmce.c1155 case MSR_F10_MC4_MISC1: in x86_mc_msrinject_verify()
/xen-4.10.0-shim-comet/xen/include/asm-x86/
A Dmsr-index.h217 #define MSR_F10_MC4_MISC1 0xc0000408 macro
/xen-4.10.0-shim-comet/xen/arch/x86/hvm/svm/
A Dsvm.c1847 case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3: in svm_msr_read_intercept()
2060 case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3: in svm_msr_write_intercept()

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