Searched refs:MSR_IA32_MCx_MISC (Results 1 – 4 of 4) sorted by relevance
146 value = mca_rdmsr(MSR_IA32_MCx_MISC(4)); in mce_amd_work_fn()176 mca_wrmsr(MSR_IA32_MCx_MISC(4), value); in mce_amd_work_fn()218 rdmsrl(MSR_IA32_MCx_MISC(4), value); in amd_nonfatal_mcheck_init()239 wrmsrl(MSR_IA32_MCx_MISC(4), value); in amd_nonfatal_mcheck_init()
163 mca_wrmsr(MSR_IA32_MCx_MISC(banknum), 0x0ULL); in mcabank_clear()214 mib->mc_misc = mca_rdmsr(MSR_IA32_MCx_MISC(bank)); in mca_init_bank()1106 (r) <= MSR_IA32_MCx_MISC(nr_mce_banks - 1) && \
118 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) macro
1846 case MSR_IA32_MCx_MISC(4): /* Threshold register */ in svm_msr_read_intercept()2059 case MSR_IA32_MCx_MISC(4): /* Threshold register */ in svm_msr_write_intercept()
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