Searched refs:MSR_IA32_MISC_ENABLE (Results 1 – 10 of 10) sorted by relevance
| /xen-4.10.0-shim-comet/xen/arch/x86/cpu/ |
| A D | intel.c | 240 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); in early_init_intel()
245 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & ~disable); in early_init_intel()
282 rdmsr (MSR_IA32_MISC_ENABLE, lo, hi); in Intel_errata_workarounds()
287 wrmsr (MSR_IA32_MISC_ENABLE, lo, hi); in Intel_errata_workarounds()
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| A D | vpmu_intel.c | 746 else if ( msr == MSR_IA32_MISC_ENABLE ) in core2_vpmu_do_rdmsr()
883 rdmsrl(MSR_IA32_MISC_ENABLE, msr_content); in vmx_vpmu_initialise()
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| A D | vpmu.c | 177 if ( !is_write && (msr != MSR_IA32_MISC_ENABLE) ) in vpmu_do_msr()
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| /xen-4.10.0-shim-comet/xen/arch/x86/cpu/mcheck/ |
| A D | mce_intel.c | 124 rdmsrl(MSR_IA32_MISC_ENABLE, msr_content); in intel_init_thermal()
170 rdmsrl(MSR_IA32_MISC_ENABLE, msr_content); in intel_init_thermal()
171 wrmsrl(MSR_IA32_MISC_ENABLE, msr_content | (1ULL<<3)); in intel_init_thermal()
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| /xen-4.10.0-shim-comet/xen/arch/x86/boot/ |
| A D | trampoline.S | 125 mov $MSR_IA32_MISC_ENABLE,%ecx
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| /xen-4.10.0-shim-comet/xen/include/asm-x86/ |
| A D | msr-index.h | 329 #define MSR_IA32_MISC_ENABLE 0x000001a0 macro
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| /xen-4.10.0-shim-comet/xen/arch/x86/ |
| A D | nmi.c | 346 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); in setup_p4_watchdog()
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| /xen-4.10.0-shim-comet/xen/arch/x86/oprofile/ |
| A D | op_model_p4.c | 542 rdmsrl(MSR_IA32_MISC_ENABLE, msr_content); in p4_setup_ctrs()
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| /xen-4.10.0-shim-comet/xen/arch/x86/pv/ |
| A D | emul-priv-op.c | 930 case MSR_IA32_MISC_ENABLE: in read_msr()
1100 case MSR_IA32_MISC_ENABLE: in write_msr()
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| /xen-4.10.0-shim-comet/xen/arch/x86/hvm/vmx/ |
| A D | vmx.c | 2915 case MSR_IA32_MISC_ENABLE: in vmx_msr_read_intercept()
2916 rdmsrl(MSR_IA32_MISC_ENABLE, *msr_content); in vmx_msr_read_intercept()
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