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Searched refs:MSR_IA32_MTRR_PHYSBASE (Results 1 – 5 of 5) sorted by relevance

/xen-4.10.0-shim-comet/xen/arch/x86/cpu/mtrr/
A Dgeneric.c32 rdmsrl(MSR_IA32_MTRR_PHYSBASE(index), vr->base); in get_mtrr_var_range()
290 rdmsrl(MSR_IA32_MTRR_PHYSBASE(reg), _base); in generic_get_mtrr()
328 rdmsrl(MSR_IA32_MTRR_PHYSBASE(index), msr_content); in set_mtrr_var_ranges()
340 mtrr_wrmsr(MSR_IA32_MTRR_PHYSBASE(index), vr->base); in set_mtrr_var_ranges()
498 mtrr_wrmsr(MSR_IA32_MTRR_PHYSBASE(reg), vr->base); in generic_set_mtrr()
/xen-4.10.0-shim-comet/xen/include/asm-x86/
A Dmsr-index.h99 #define MSR_IA32_MTRR_PHYSBASE(n) (0x00000200 + 2 * (n)) macro
/xen-4.10.0-shim-comet/xen/arch/x86/hvm/
A Dmtrr.c447 index = msr - MSR_IA32_MTRR_PHYSBASE(0); in mtrr_var_range_msr_set()
736 MSR_IA32_MTRR_PHYSBASE(i), in hvm_load_mtrr_msr()
A Dhvm.c3486 case MSR_IA32_MTRR_PHYSBASE(0)...MSR_IA32_MTRR_PHYSMASK(MTRR_VCNT-1): in hvm_msr_read_intercept()
3489 index = msr - MSR_IA32_MTRR_PHYSBASE(0); in hvm_msr_read_intercept()
3641 case MSR_IA32_MTRR_PHYSBASE(0)...MSR_IA32_MTRR_PHYSMASK(MTRR_VCNT-1): in hvm_msr_write_intercept()
/xen-4.10.0-shim-comet/xen/arch/x86/
A De820.c479 rdmsrl(MSR_IA32_MTRR_PHYSBASE(i), base); in mtrr_top_of_ram()

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