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Searched refs:MSR_IA32_MTRR_PHYSMASK (Results 1 – 5 of 5) sorted by relevance

/xen-4.10.0-shim-comet/xen/arch/x86/cpu/mtrr/
A Dgeneric.c33 rdmsrl(MSR_IA32_MTRR_PHYSMASK(index), vr->mask); in get_mtrr_var_range()
281 rdmsrl(MSR_IA32_MTRR_PHYSMASK(reg), _mask); in generic_get_mtrr()
344 rdmsrl(MSR_IA32_MTRR_PHYSMASK(index), msr_content); in set_mtrr_var_ranges()
356 mtrr_wrmsr(MSR_IA32_MTRR_PHYSMASK(index), vr->mask); in set_mtrr_var_ranges()
487 mtrr_wrmsr(MSR_IA32_MTRR_PHYSMASK(reg), 0); in generic_set_mtrr()
499 mtrr_wrmsr(MSR_IA32_MTRR_PHYSMASK(reg), vr->mask); in generic_set_mtrr()
/xen-4.10.0-shim-comet/xen/include/asm-x86/
A Dmsr-index.h100 #define MSR_IA32_MTRR_PHYSMASK(n) (0x00000201 + 2 * (n)) macro
/xen-4.10.0-shim-comet/xen/arch/x86/
A De820.c480 rdmsrl(MSR_IA32_MTRR_PHYSMASK(i), mask); in mtrr_top_of_ram()
/xen-4.10.0-shim-comet/xen/arch/x86/hvm/
A Dmtrr.c739 MSR_IA32_MTRR_PHYSMASK(i), in hvm_load_mtrr_msr()
A Dhvm.c3486 case MSR_IA32_MTRR_PHYSBASE(0)...MSR_IA32_MTRR_PHYSMASK(MTRR_VCNT-1): in hvm_msr_read_intercept()
3641 case MSR_IA32_MTRR_PHYSBASE(0)...MSR_IA32_MTRR_PHYSMASK(MTRR_VCNT-1): in hvm_msr_write_intercept()

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