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Searched refs:MSR_P4_BPU_PERFCTR0 (Results 1 – 3 of 3) sorted by relevance

/xen-4.10.0-shim-comet/xen/include/asm-x86/
A Dmsr-index.h378 #define MSR_P4_BPU_PERFCTR0 0x00000300 macro
/xen-4.10.0-shim-comet/xen/arch/x86/
A Dnmi.c370 clear_msr_range(MSR_P4_BPU_PERFCTR0, 18); in setup_p4_watchdog()
/xen-4.10.0-shim-comet/xen/arch/x86/oprofile/
A Dop_model_p4.c83 { CTR_BPU_0, MSR_P4_BPU_PERFCTR0, MSR_P4_BPU_CCCR0 },

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