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Searched refs:MSR_P4_TBPU_ESCR0 (Results 1 – 2 of 2) sorted by relevance

/xen-4.10.0-shim-comet/xen/arch/x86/oprofile/
A Dop_model_p4.c332 { { CTR_MS_0, MSR_P4_TBPU_ESCR0},
338 { { CTR_MS_0, MSR_P4_TBPU_ESCR0},
/xen-4.10.0-shim-comet/xen/include/asm-x86/
A Dmsr-index.h455 #define MSR_P4_TBPU_ESCR0 0x000003c2 macro

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