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Searched refs:READ_SYSREG32 (Results 1 – 11 of 11) sorted by relevance

/xen-4.10.0-shim-comet/xen/arch/arm/
A Dcpu.c21 c->midr.bits = READ_SYSREG32(MIDR_EL1); in identify_cpu()
41 c->pfr32.bits[0] = READ_SYSREG32(ID_PFR0_EL1); in identify_cpu()
42 c->pfr32.bits[1] = READ_SYSREG32(ID_PFR1_EL1); in identify_cpu()
44 c->dbg32.bits[0] = READ_SYSREG32(ID_DFR0_EL1); in identify_cpu()
46 c->aux32.bits[0] = READ_SYSREG32(ID_AFR0_EL1); in identify_cpu()
48 c->mm32.bits[0] = READ_SYSREG32(ID_MMFR0_EL1); in identify_cpu()
49 c->mm32.bits[1] = READ_SYSREG32(ID_MMFR1_EL1); in identify_cpu()
50 c->mm32.bits[2] = READ_SYSREG32(ID_MMFR2_EL1); in identify_cpu()
51 c->mm32.bits[3] = READ_SYSREG32(ID_MMFR3_EL1); in identify_cpu()
53 c->isa32.bits[0] = READ_SYSREG32(ID_ISAR0_EL1); in identify_cpu()
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A Dtime.c147 cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; in preinit_xen_time()
225 READ_SYSREG32(CNTHP_CTL_EL2) & CNTx_CTL_PENDING ) in timer_interrupt()
235 READ_SYSREG32(CNTP_CTL_EL0) & CNTx_CTL_PENDING ) in timer_interrupt()
262 current->arch.virt_timer.ctl = READ_SYSREG32(CNTV_CTL_EL0); in vtimer_interrupt()
A Dgic-v3.c253 val = READ_SYSREG32(ICC_SRE_EL2); in gicv3_enable_sre()
343 d->v3.apr0[2] = READ_SYSREG32(ICH_AP0R2_EL2); in save_aprn_regs()
344 d->v3.apr1[2] = READ_SYSREG32(ICH_AP1R2_EL2); in save_aprn_regs()
384 val = READ_SYSREG32(ICC_SRE_EL2); in gicv3_restore_state()
471 unsigned int irq = READ_SYSREG32(ICC_IAR1_EL1); in gicv3_read_irq()
830 vtr = READ_SYSREG32(ICH_VTR_EL2); in gicv3_hyp_init()
861 hcr = READ_SYSREG32(ICH_HCR_EL2); in gicv3_hyp_disable()
1030 hcr = READ_SYSREG32(ICH_HCR_EL2); in gicv3_hcr_status()
1051 return READ_SYSREG32(ICH_AP1R0_EL2); in gicv3_read_apr()
1054 return READ_SYSREG32(ICH_AP1R1_EL2); in gicv3_read_apr()
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A Ddomain.c113 p->arch.cntkctl = READ_SYSREG32(CNTKCTL_EL1); in ctxt_switch_from()
118 p->arch.teecr = READ_SYSREG32(TEECR32_EL1); in ctxt_switch_from()
119 p->arch.teehbr = READ_SYSREG32(TEEHBR32_EL1); in ctxt_switch_from()
543 v->arch.actlr = READ_SYSREG32(ACTLR_EL1); in vcpu_initialise()
A Dvtimer.c144 v->arch.virt_timer.ctl = READ_SYSREG32(CNTV_CTL_EL0); in virt_timer_save()
A Dtraps.c407 uint32_t sctlr = READ_SYSREG32(SCTLR_EL1); in cpsr_switch_mode()
423 uint32_t sctlr = READ_SYSREG32(SCTLR_EL1); in exception_handler32()
963 printk(" VTCR_EL2: %08"PRIx32"\n", READ_SYSREG32(VTCR_EL2)); in _show_registers()
967 printk(" SCTLR_EL2: %08"PRIx32"\n", READ_SYSREG32(SCTLR_EL2)); in _show_registers()
A Dmm.c722 WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2); in setup_pagetables()
797 WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2); in mmu_init_secondary_cpu()
A Dsetup.c692 ccsid = READ_SYSREG32(CCSIDR_EL1); in setup_cache()
/xen-4.10.0-shim-comet/xen/arch/arm/arm64/
A Dvfp.c29 v->arch.vfp.fpsr = READ_SYSREG32(FPSR); in vfp_save_state()
30 v->arch.vfp.fpcr = READ_SYSREG32(FPCR); in vfp_save_state()
32 v->arch.vfp.fpexc32_el2 = READ_SYSREG32(FPEXC32_EL2); in vfp_save_state()
/xen-4.10.0-shim-comet/xen/include/asm-arm/arm32/
A Dprocessor.h112 #define READ_SYSREG32(R...) READ_CP32(R) macro
118 #define READ_SYSREG(R...) READ_SYSREG32(R)
/xen-4.10.0-shim-comet/xen/include/asm-arm/arm64/
A Dprocessor.h94 #define READ_SYSREG32(name) ({ \ macro

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