1 #ifndef __ASM_ARM_PROCESSOR_H 2 #define __ASM_ARM_PROCESSOR_H 3 4 #ifndef __ASSEMBLY__ 5 #include <xen/types.h> 6 #endif 7 #include <public/arch-arm.h> 8 9 /* MIDR Main ID Register */ 10 #define MIDR_REVISION_MASK 0xf 11 #define MIDR_RESIVION(midr) ((midr) & MIDR_REVISION_MASK) 12 #define MIDR_PARTNUM_SHIFT 4 13 #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) 14 #define MIDR_PARTNUM(midr) \ 15 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) 16 #define MIDR_ARCHITECTURE_SHIFT 16 17 #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) 18 #define MIDR_ARCHITECTURE(midr) \ 19 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) 20 #define MIDR_VARIANT_SHIFT 20 21 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) 22 #define MIDR_VARIANT(midr) \ 23 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) 24 #define MIDR_IMPLEMENTOR_SHIFT 24 25 #define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) 26 #define MIDR_IMPLEMENTOR(midr) \ 27 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) 28 29 #define MIDR_CPU_MODEL(imp, partnum) \ 30 (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ 31 (0xf << MIDR_ARCHITECTURE_SHIFT) | \ 32 ((partnum) << MIDR_PARTNUM_SHIFT)) 33 34 #define MIDR_CPU_MODEL_MASK \ 35 (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | MIDR_ARCHITECTURE_MASK) 36 37 #define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \ 38 ({ \ 39 u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \ 40 u32 _rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \ 41 \ 42 _model == (model) && _rv >= (rv_min) && _rv <= (rv_max); \ 43 }) 44 45 #define ARM_CPU_IMP_ARM 0x41 46 47 #define ARM_CPU_PART_CORTEX_A15 0xC0F 48 #define ARM_CPU_PART_CORTEX_A53 0xD03 49 #define ARM_CPU_PART_CORTEX_A57 0xD07 50 51 #define MIDR_CORTEX_A15 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A15) 52 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) 53 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) 54 55 /* MPIDR Multiprocessor Affinity Register */ 56 #define _MPIDR_UP (30) 57 #define MPIDR_UP (_AC(1,U) << _MPIDR_UP) 58 #define _MPIDR_SMP (31) 59 #define MPIDR_SMP (_AC(1,U) << _MPIDR_SMP) 60 #define MPIDR_AFF0_SHIFT (0) 61 #define MPIDR_AFF0_MASK (_AC(0xff,U) << MPIDR_AFF0_SHIFT) 62 #ifdef CONFIG_ARM_64 63 #define MPIDR_HWID_MASK _AC(0xff00ffffff,UL) 64 #else 65 #define MPIDR_HWID_MASK _AC(0xffffff,U) 66 #endif 67 #define MPIDR_INVALID (~MPIDR_HWID_MASK) 68 #define MPIDR_LEVEL_BITS (8) 69 70 71 /* 72 * Macros to extract affinity level. picked from kernel 73 */ 74 75 #define MPIDR_LEVEL_BITS_SHIFT 3 76 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) 77 78 #define MPIDR_LEVEL_SHIFT(level) \ 79 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT) 80 81 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ 82 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) 83 84 #define AFFINITY_MASK(level) ~((_AC(0x1,UL) << MPIDR_LEVEL_SHIFT(level)) - 1) 85 86 /* TTBCR Translation Table Base Control Register */ 87 #define TTBCR_EAE _AC(0x80000000,U) 88 #define TTBCR_N_MASK _AC(0x07,U) 89 #define TTBCR_N_16KB _AC(0x00,U) 90 #define TTBCR_N_8KB _AC(0x01,U) 91 #define TTBCR_N_4KB _AC(0x02,U) 92 #define TTBCR_N_2KB _AC(0x03,U) 93 #define TTBCR_N_1KB _AC(0x04,U) 94 95 /* 96 * TTBCR_PD(0|1) can be applied only if LPAE is disabled, i.e., TTBCR.EAE==0 97 * (ARM DDI 0487B.a G6-5203 and ARM DDI 0406C.b B4-1722). 98 */ 99 #define TTBCR_PD0 (_AC(1,U)<<4) 100 #define TTBCR_PD1 (_AC(1,U)<<5) 101 102 /* SCTLR System Control Register. */ 103 /* HSCTLR is a subset of this. */ 104 #define SCTLR_TE (_AC(1,U)<<30) 105 #define SCTLR_AFE (_AC(1,U)<<29) 106 #define SCTLR_TRE (_AC(1,U)<<28) 107 #define SCTLR_NMFI (_AC(1,U)<<27) 108 #define SCTLR_EE (_AC(1,U)<<25) 109 #define SCTLR_VE (_AC(1,U)<<24) 110 #define SCTLR_U (_AC(1,U)<<22) 111 #define SCTLR_FI (_AC(1,U)<<21) 112 #define SCTLR_WXN (_AC(1,U)<<19) 113 #define SCTLR_HA (_AC(1,U)<<17) 114 #define SCTLR_RR (_AC(1,U)<<14) 115 #define SCTLR_V (_AC(1,U)<<13) 116 #define SCTLR_I (_AC(1,U)<<12) 117 #define SCTLR_Z (_AC(1,U)<<11) 118 #define SCTLR_SW (_AC(1,U)<<10) 119 #define SCTLR_B (_AC(1,U)<<7) 120 #define SCTLR_C (_AC(1,U)<<2) 121 #define SCTLR_A (_AC(1,U)<<1) 122 #define SCTLR_M (_AC(1,U)<<0) 123 124 #define HSCTLR_BASE _AC(0x30c51878,U) 125 126 /* HCR Hyp Configuration Register */ 127 #define HCR_RW (_AC(1,UL)<<31) /* Register Width, ARM64 only */ 128 #define HCR_TGE (_AC(1,UL)<<27) /* Trap General Exceptions */ 129 #define HCR_TVM (_AC(1,UL)<<26) /* Trap Virtual Memory Controls */ 130 #define HCR_TTLB (_AC(1,UL)<<25) /* Trap TLB Maintenance Operations */ 131 #define HCR_TPU (_AC(1,UL)<<24) /* Trap Cache Maintenance Operations to PoU */ 132 #define HCR_TPC (_AC(1,UL)<<23) /* Trap Cache Maintenance Operations to PoC */ 133 #define HCR_TSW (_AC(1,UL)<<22) /* Trap Set/Way Cache Maintenance Operations */ 134 #define HCR_TAC (_AC(1,UL)<<21) /* Trap ACTLR Accesses */ 135 #define HCR_TIDCP (_AC(1,UL)<<20) /* Trap lockdown */ 136 #define HCR_TSC (_AC(1,UL)<<19) /* Trap SMC instruction */ 137 #define HCR_TID3 (_AC(1,UL)<<18) /* Trap ID Register Group 3 */ 138 #define HCR_TID2 (_AC(1,UL)<<17) /* Trap ID Register Group 2 */ 139 #define HCR_TID1 (_AC(1,UL)<<16) /* Trap ID Register Group 1 */ 140 #define HCR_TID0 (_AC(1,UL)<<15) /* Trap ID Register Group 0 */ 141 #define HCR_TWE (_AC(1,UL)<<14) /* Trap WFE instruction */ 142 #define HCR_TWI (_AC(1,UL)<<13) /* Trap WFI instruction */ 143 #define HCR_DC (_AC(1,UL)<<12) /* Default cacheable */ 144 #define HCR_BSU_MASK (_AC(3,UL)<<10) /* Barrier Shareability Upgrade */ 145 #define HCR_BSU_NONE (_AC(0,UL)<<10) 146 #define HCR_BSU_INNER (_AC(1,UL)<<10) 147 #define HCR_BSU_OUTER (_AC(2,UL)<<10) 148 #define HCR_BSU_FULL (_AC(3,UL)<<10) 149 #define HCR_FB (_AC(1,UL)<<9) /* Force Broadcast of Cache/BP/TLB operations */ 150 #define HCR_VA (_AC(1,UL)<<8) /* Virtual Asynchronous Abort */ 151 #define HCR_VI (_AC(1,UL)<<7) /* Virtual IRQ */ 152 #define HCR_VF (_AC(1,UL)<<6) /* Virtual FIQ */ 153 #define HCR_AMO (_AC(1,UL)<<5) /* Override CPSR.A */ 154 #define HCR_IMO (_AC(1,UL)<<4) /* Override CPSR.I */ 155 #define HCR_FMO (_AC(1,UL)<<3) /* Override CPSR.F */ 156 #define HCR_PTW (_AC(1,UL)<<2) /* Protected Walk */ 157 #define HCR_SWIO (_AC(1,UL)<<1) /* Set/Way Invalidation Override */ 158 #define HCR_VM (_AC(1,UL)<<0) /* Virtual MMU Enable */ 159 160 /* TCR: Stage 1 Translation Control */ 161 162 #define TCR_T0SZ_SHIFT (0) 163 #define TCR_T1SZ_SHIFT (16) 164 #define TCR_T0SZ(x) ((x)<<TCR_T0SZ_SHIFT) 165 166 /* 167 * According to ARM DDI 0487B.a, TCR_EL1.{T0SZ,T1SZ} (AArch64, page D7-2480) 168 * comprises 6 bits and TTBCR.{T0SZ,T1SZ} (AArch32, page G6-5204) comprises 3 169 * bits following another 3 bits for RES0. Thus, the mask for both registers 170 * should be 0x3f. 171 */ 172 #define TCR_SZ_MASK (_AC(0x3f,UL)) 173 174 #define TCR_EPD0 (_AC(0x1,UL)<<7) 175 #define TCR_EPD1 (_AC(0x1,UL)<<23) 176 177 #define TCR_IRGN0_NC (_AC(0x0,UL)<<8) 178 #define TCR_IRGN0_WBWA (_AC(0x1,UL)<<8) 179 #define TCR_IRGN0_WT (_AC(0x2,UL)<<8) 180 #define TCR_IRGN0_WB (_AC(0x3,UL)<<8) 181 182 #define TCR_ORGN0_NC (_AC(0x0,UL)<<10) 183 #define TCR_ORGN0_WBWA (_AC(0x1,UL)<<10) 184 #define TCR_ORGN0_WT (_AC(0x2,UL)<<10) 185 #define TCR_ORGN0_WB (_AC(0x3,UL)<<10) 186 187 #define TCR_SH0_NS (_AC(0x0,UL)<<12) 188 #define TCR_SH0_OS (_AC(0x2,UL)<<12) 189 #define TCR_SH0_IS (_AC(0x3,UL)<<12) 190 191 /* Note that the fields TCR_EL1.{TG0,TG1} are not available on AArch32. */ 192 #define TCR_TG0_SHIFT (14) 193 #define TCR_TG0_MASK (_AC(0x3,UL)<<TCR_TG0_SHIFT) 194 #define TCR_TG0_4K (_AC(0x0,UL)<<TCR_TG0_SHIFT) 195 #define TCR_TG0_64K (_AC(0x1,UL)<<TCR_TG0_SHIFT) 196 #define TCR_TG0_16K (_AC(0x2,UL)<<TCR_TG0_SHIFT) 197 198 /* Note that the field TCR_EL2.TG1 exists only if HCR_EL2.E2H==1. */ 199 #define TCR_EL1_TG1_SHIFT (30) 200 #define TCR_EL1_TG1_MASK (_AC(0x3,UL)<<TCR_EL1_TG1_SHIFT) 201 #define TCR_EL1_TG1_16K (_AC(0x1,UL)<<TCR_EL1_TG1_SHIFT) 202 #define TCR_EL1_TG1_4K (_AC(0x2,UL)<<TCR_EL1_TG1_SHIFT) 203 #define TCR_EL1_TG1_64K (_AC(0x3,UL)<<TCR_EL1_TG1_SHIFT) 204 205 /* 206 * Note that the field TCR_EL1.IPS is not available on AArch32. Also, the field 207 * TCR_EL2.IPS exists only if HCR_EL2.E2H==1. 208 */ 209 #define TCR_EL1_IPS_SHIFT (32) 210 #define TCR_EL1_IPS_MASK (_AC(0x7,ULL)<<TCR_EL1_IPS_SHIFT) 211 #define TCR_EL1_IPS_32_BIT (_AC(0x0,ULL)<<TCR_EL1_IPS_SHIFT) 212 #define TCR_EL1_IPS_36_BIT (_AC(0x1,ULL)<<TCR_EL1_IPS_SHIFT) 213 #define TCR_EL1_IPS_40_BIT (_AC(0x2,ULL)<<TCR_EL1_IPS_SHIFT) 214 #define TCR_EL1_IPS_42_BIT (_AC(0x3,ULL)<<TCR_EL1_IPS_SHIFT) 215 #define TCR_EL1_IPS_44_BIT (_AC(0x4,ULL)<<TCR_EL1_IPS_SHIFT) 216 #define TCR_EL1_IPS_48_BIT (_AC(0x5,ULL)<<TCR_EL1_IPS_SHIFT) 217 #define TCR_EL1_IPS_52_BIT (_AC(0x6,ULL)<<TCR_EL1_IPS_SHIFT) 218 219 /* 220 * The following values correspond to the bit masks represented by 221 * TCR_EL1_IPS_XX_BIT defines. 222 */ 223 #define TCR_EL1_IPS_32_BIT_VAL (32) 224 #define TCR_EL1_IPS_36_BIT_VAL (36) 225 #define TCR_EL1_IPS_40_BIT_VAL (40) 226 #define TCR_EL1_IPS_42_BIT_VAL (42) 227 #define TCR_EL1_IPS_44_BIT_VAL (44) 228 #define TCR_EL1_IPS_48_BIT_VAL (48) 229 #define TCR_EL1_IPS_52_BIT_VAL (52) 230 #define TCR_EL1_IPS_MIN_VAL (25) 231 232 /* Note that the fields TCR_EL2.TBI(0|1) exist only if HCR_EL2.E2H==1. */ 233 #define TCR_EL1_TBI0 (_AC(0x1,ULL)<<37) 234 #define TCR_EL1_TBI1 (_AC(0x1,ULL)<<38) 235 236 #ifdef CONFIG_ARM_64 237 238 #define TCR_PS(x) ((x)<<16) 239 #define TCR_TBI (_AC(0x1,UL)<<20) 240 241 #define TCR_RES1 (_AC(1,UL)<<31|_AC(1,UL)<<23) 242 243 #else 244 245 #define TCR_RES1 (_AC(1,UL)<<31) 246 247 #endif 248 249 /* VTCR: Stage 2 Translation Control */ 250 251 #define VTCR_T0SZ(x) ((x)<<0) 252 253 #define VTCR_SL0(x) ((x)<<6) 254 255 #define VTCR_IRGN0_NC (_AC(0x0,UL)<<8) 256 #define VTCR_IRGN0_WBWA (_AC(0x1,UL)<<8) 257 #define VTCR_IRGN0_WT (_AC(0x2,UL)<<8) 258 #define VTCR_IRGN0_WB (_AC(0x3,UL)<<8) 259 260 #define VTCR_ORGN0_NC (_AC(0x0,UL)<<10) 261 #define VTCR_ORGN0_WBWA (_AC(0x1,UL)<<10) 262 #define VTCR_ORGN0_WT (_AC(0x2,UL)<<10) 263 #define VTCR_ORGN0_WB (_AC(0x3,UL)<<10) 264 265 #define VTCR_SH0_NS (_AC(0x0,UL)<<12) 266 #define VTCR_SH0_OS (_AC(0x2,UL)<<12) 267 #define VTCR_SH0_IS (_AC(0x3,UL)<<12) 268 269 #ifdef CONFIG_ARM_64 270 271 #define VTCR_TG0_4K (_AC(0x0,UL)<<14) 272 #define VTCR_TG0_64K (_AC(0x1,UL)<<14) 273 #define VTCR_TG0_16K (_AC(0x2,UL)<<14) 274 275 #define VTCR_PS(x) ((x)<<16) 276 277 #define VTCR_VS (_AC(0x1,UL)<<19) 278 279 #endif 280 281 #define VTCR_RES1 (_AC(1,UL)<<31) 282 283 /* HCPTR Hyp. Coprocessor Trap Register */ 284 #define HCPTR_TTA ((_AC(1,U)<<20)) /* Trap trace registers */ 285 #define HCPTR_CP(x) ((_AC(1,U)<<(x))) /* Trap Coprocessor x */ 286 #define HCPTR_CP_MASK ((_AC(1,U)<<14)-1) 287 288 /* HSTR Hyp. System Trap Register */ 289 #define HSTR_T(x) ((_AC(1,U)<<(x))) /* Trap Cp15 c<x> */ 290 291 /* HDCR Hyp. Debug Configuration Register */ 292 #define HDCR_TDRA (_AC(1,U)<<11) /* Trap Debug ROM access */ 293 #define HDCR_TDOSA (_AC(1,U)<<10) /* Trap Debug-OS-related register access */ 294 #define HDCR_TDA (_AC(1,U)<<9) /* Trap Debug Access */ 295 #define HDCR_TDE (_AC(1,U)<<8) /* Route Soft Debug exceptions from EL1/EL1 to EL2 */ 296 #define HDCR_TPM (_AC(1,U)<<6) /* Trap Performance Monitors accesses */ 297 #define HDCR_TPMCR (_AC(1,U)<<5) /* Trap PMCR accesses */ 298 299 #define HSR_EC_UNKNOWN 0x00 300 #define HSR_EC_WFI_WFE 0x01 301 #define HSR_EC_CP15_32 0x03 302 #define HSR_EC_CP15_64 0x04 303 #define HSR_EC_CP14_32 0x05 /* Trapped MCR or MRC access to CP14 */ 304 #define HSR_EC_CP14_DBG 0x06 /* Trapped LDC/STC access to CP14 (only for debug registers) */ 305 #define HSR_EC_CP 0x07 /* HCPTR-trapped access to CP0-CP13 */ 306 #define HSR_EC_CP10 0x08 307 #define HSR_EC_JAZELLE 0x09 308 #define HSR_EC_BXJ 0x0a 309 #define HSR_EC_CP14_64 0x0c 310 #define HSR_EC_SVC32 0x11 311 #define HSR_EC_HVC32 0x12 312 #define HSR_EC_SMC32 0x13 313 #ifdef CONFIG_ARM_64 314 #define HSR_EC_SVC64 0x15 315 #define HSR_EC_HVC64 0x16 316 #define HSR_EC_SMC64 0x17 317 #define HSR_EC_SYSREG 0x18 318 #endif 319 #define HSR_EC_INSTR_ABORT_LOWER_EL 0x20 320 #define HSR_EC_INSTR_ABORT_CURR_EL 0x21 321 #define HSR_EC_DATA_ABORT_LOWER_EL 0x24 322 #define HSR_EC_DATA_ABORT_CURR_EL 0x25 323 #ifdef CONFIG_ARM_64 324 #define HSR_EC_BRK 0x3c 325 #endif 326 327 /* FSR format, common */ 328 #define FSR_LPAE (_AC(1,UL)<<9) 329 /* FSR short format */ 330 #define FSRS_FS_DEBUG (_AC(0,UL)<<10|_AC(0x2,UL)<<0) 331 /* FSR long format */ 332 #define FSRL_STATUS_DEBUG (_AC(0x22,UL)<<0) 333 334 #ifdef CONFIG_ARM_64 335 #define MM64_VMID_8_BITS_SUPPORT 0x0 336 #define MM64_VMID_16_BITS_SUPPORT 0x2 337 #endif 338 339 #ifndef __ASSEMBLY__ 340 341 struct cpuinfo_arm { 342 union { 343 uint32_t bits; 344 struct { 345 unsigned long revision:4; 346 unsigned long part_number:12; 347 unsigned long architecture:4; 348 unsigned long variant:4; 349 unsigned long implementer:8; 350 }; 351 } midr; 352 union { 353 register_t bits; 354 struct { 355 unsigned long aff0:8; 356 unsigned long aff1:8; 357 unsigned long aff2:8; 358 unsigned long mt:1; /* Multi-thread, iff MP == 1 */ 359 unsigned long __res0:5; 360 unsigned long up:1; /* UP system, iff MP == 1 */ 361 unsigned long mp:1; /* MP extensions */ 362 363 #ifdef CONFIG_ARM_64 364 unsigned long aff3:8; 365 unsigned long __res1:24; 366 #endif 367 }; 368 } mpidr; 369 370 #ifdef CONFIG_ARM_64 371 /* 64-bit CPUID registers. */ 372 union { 373 uint64_t bits[2]; 374 struct { 375 unsigned long el0:4; 376 unsigned long el1:4; 377 unsigned long el2:4; 378 unsigned long el3:4; 379 unsigned long fp:4; /* Floating Point */ 380 unsigned long simd:4; /* Advanced SIMD */ 381 unsigned long gic:4; /* GIC support */ 382 unsigned long __res0:4; 383 unsigned long __res1; 384 }; 385 } pfr64; 386 387 struct { 388 uint64_t bits[2]; 389 } dbg64; 390 391 struct { 392 uint64_t bits[2]; 393 } aux64; 394 395 union { 396 uint64_t bits[2]; 397 struct { 398 unsigned long pa_range:4; 399 unsigned long asid_bits:4; 400 unsigned long bigend:4; 401 unsigned long secure_ns:4; 402 unsigned long bigend_el0:4; 403 unsigned long tgranule_16K:4; 404 unsigned long tgranule_64K:4; 405 unsigned long tgranule_4K:4; 406 unsigned long __res0:32; 407 408 unsigned long hafdbs:4; 409 unsigned long vmid_bits:4; 410 unsigned long vh:4; 411 unsigned long hpds:4; 412 unsigned long lo:4; 413 unsigned long pan:4; 414 unsigned long __res1:8; 415 unsigned long __res2:32; 416 }; 417 } mm64; 418 419 struct { 420 uint64_t bits[2]; 421 } isa64; 422 423 #endif 424 425 /* 426 * 32-bit CPUID registers. On ARMv8 these describe the properties 427 * when running in 32-bit mode. 428 */ 429 union { 430 uint32_t bits[2]; 431 struct { 432 unsigned long arm:4; 433 unsigned long thumb:4; 434 unsigned long jazelle:4; 435 unsigned long thumbee:4; 436 unsigned long __res0:16; 437 438 unsigned long progmodel:4; 439 unsigned long security:4; 440 unsigned long mprofile:4; 441 unsigned long virt:4; 442 unsigned long gentimer:4; 443 unsigned long __res1:12; 444 }; 445 } pfr32; 446 447 struct { 448 uint32_t bits[1]; 449 } dbg32; 450 451 struct { 452 uint32_t bits[1]; 453 } aux32; 454 455 struct { 456 uint32_t bits[4]; 457 } mm32; 458 459 struct { 460 uint32_t bits[6]; 461 } isa32; 462 }; 463 464 /* 465 * capabilities of CPUs 466 */ 467 468 extern struct cpuinfo_arm boot_cpu_data; 469 470 extern void identify_cpu(struct cpuinfo_arm *); 471 472 extern struct cpuinfo_arm cpu_data[]; 473 #define current_cpu_data cpu_data[smp_processor_id()] 474 475 extern register_t __cpu_logical_map[]; 476 #define cpu_logical_map(cpu) __cpu_logical_map[cpu] 477 478 /* HSR data abort size definition */ 479 enum dabt_size { 480 DABT_BYTE = 0, 481 DABT_HALF_WORD = 1, 482 DABT_WORD = 2, 483 DABT_DOUBLE_WORD = 3, 484 }; 485 486 union hsr { 487 uint32_t bits; 488 struct { 489 unsigned long iss:25; /* Instruction Specific Syndrome */ 490 unsigned long len:1; /* Instruction length */ 491 unsigned long ec:6; /* Exception Class */ 492 }; 493 494 /* Common to all conditional exception classes (0x0N, except 0x00). */ 495 struct hsr_cond { 496 unsigned long iss:20; /* Instruction Specific Syndrome */ 497 unsigned long cc:4; /* Condition Code */ 498 unsigned long ccvalid:1;/* CC Valid */ 499 unsigned long len:1; /* Instruction length */ 500 unsigned long ec:6; /* Exception Class */ 501 } cond; 502 503 struct hsr_wfi_wfe { 504 unsigned long ti:1; /* Trapped instruction */ 505 unsigned long sbzp:19; 506 unsigned long cc:4; /* Condition Code */ 507 unsigned long ccvalid:1;/* CC Valid */ 508 unsigned long len:1; /* Instruction length */ 509 unsigned long ec:6; /* Exception Class */ 510 } wfi_wfe; 511 512 /* reg, reg0, reg1 are 4 bits on AArch32, the fifth bit is sbzp. */ 513 struct hsr_cp32 { 514 unsigned long read:1; /* Direction */ 515 unsigned long crm:4; /* CRm */ 516 unsigned long reg:5; /* Rt */ 517 unsigned long crn:4; /* CRn */ 518 unsigned long op1:3; /* Op1 */ 519 unsigned long op2:3; /* Op2 */ 520 unsigned long cc:4; /* Condition Code */ 521 unsigned long ccvalid:1;/* CC Valid */ 522 unsigned long len:1; /* Instruction length */ 523 unsigned long ec:6; /* Exception Class */ 524 } cp32; /* HSR_EC_CP15_32, CP14_32, CP10 */ 525 526 struct hsr_cp64 { 527 unsigned long read:1; /* Direction */ 528 unsigned long crm:4; /* CRm */ 529 unsigned long reg1:5; /* Rt1 */ 530 unsigned long reg2:5; /* Rt2 */ 531 unsigned long sbzp2:1; 532 unsigned long op1:4; /* Op1 */ 533 unsigned long cc:4; /* Condition Code */ 534 unsigned long ccvalid:1;/* CC Valid */ 535 unsigned long len:1; /* Instruction length */ 536 unsigned long ec:6; /* Exception Class */ 537 } cp64; /* HSR_EC_CP15_64, HSR_EC_CP14_64 */ 538 539 struct hsr_cp { 540 unsigned long coproc:4; /* Number of coproc accessed */ 541 unsigned long sbz0p:1; 542 unsigned long tas:1; /* Trapped Advanced SIMD */ 543 unsigned long res0:14; 544 unsigned long cc:4; /* Condition Code */ 545 unsigned long ccvalid:1;/* CC Valid */ 546 unsigned long len:1; /* Instruction length */ 547 unsigned long ec:6; /* Exception Class */ 548 } cp; /* HSR_EC_CP */ 549 550 /* 551 * This encoding is valid only for ARMv8 (ARM DDI 0487B.a, pages D7-2271 and 552 * G6-4957). On ARMv7, encoding ISS for EC=0x13 is defined as UNK/SBZP 553 * (ARM DDI 0406C.c page B3-1431). UNK/SBZP means that hardware implements 554 * this field as Read-As-Zero. ARMv8 is backwards compatible with ARMv7: 555 * reading CCKNOWNPASS on ARMv7 will return 0, which means that condition 556 * check was passed or instruction was unconditional. 557 */ 558 struct hsr_smc32 { 559 unsigned long res0:19; /* Reserved */ 560 unsigned long ccknownpass:1; /* Instruction passed conditional check */ 561 unsigned long cc:4; /* Condition Code */ 562 unsigned long ccvalid:1;/* CC Valid */ 563 unsigned long len:1; /* Instruction length */ 564 unsigned long ec:6; /* Exception Class */ 565 } smc32; /* HSR_EC_SMC32 */ 566 567 #ifdef CONFIG_ARM_64 568 struct hsr_sysreg { 569 unsigned long read:1; /* Direction */ 570 unsigned long crm:4; /* CRm */ 571 unsigned long reg:5; /* Rt */ 572 unsigned long crn:4; /* CRn */ 573 unsigned long op1:3; /* Op1 */ 574 unsigned long op2:3; /* Op2 */ 575 unsigned long op0:2; /* Op0 */ 576 unsigned long res0:3; 577 unsigned long len:1; /* Instruction length */ 578 unsigned long ec:6; 579 } sysreg; /* HSR_EC_SYSREG */ 580 #endif 581 582 struct hsr_iabt { 583 unsigned long ifsc:6; /* Instruction fault status code */ 584 unsigned long res0:1; /* RES0 */ 585 unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ 586 unsigned long res1:1; /* RES0 */ 587 unsigned long eat:1; /* External abort type */ 588 unsigned long fnv:1; /* FAR not Valid */ 589 unsigned long res2:14; 590 unsigned long len:1; /* Instruction length */ 591 unsigned long ec:6; /* Exception Class */ 592 } iabt; /* HSR_EC_INSTR_ABORT_* */ 593 594 struct hsr_dabt { 595 unsigned long dfsc:6; /* Data Fault Status Code */ 596 unsigned long write:1; /* Write / not Read */ 597 unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ 598 unsigned long cache:1; /* Cache Maintenance */ 599 unsigned long eat:1; /* External Abort Type */ 600 unsigned long fnv:1; /* FAR not Valid */ 601 #ifdef CONFIG_ARM_32 602 unsigned long sbzp0:5; 603 #else 604 unsigned long sbzp0:3; 605 unsigned long ar:1; /* Acquire Release */ 606 unsigned long sf:1; /* Sixty Four bit register */ 607 #endif 608 unsigned long reg:5; /* Register */ 609 unsigned long sign:1; /* Sign extend */ 610 unsigned long size:2; /* Access Size */ 611 unsigned long valid:1; /* Syndrome Valid */ 612 unsigned long len:1; /* Instruction length */ 613 unsigned long ec:6; /* Exception Class */ 614 } dabt; /* HSR_EC_DATA_ABORT_* */ 615 616 /* Contain the common bits between DABT and IABT */ 617 struct hsr_xabt { 618 unsigned long fsc:6; /* Fault status code */ 619 unsigned long pad1:1; /* Not common */ 620 unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ 621 unsigned long pad2:1; /* Not common */ 622 unsigned long eat:1; /* External abort type */ 623 unsigned long fnv:1; /* FAR not Valid */ 624 unsigned long pad3:14; /* Not common */ 625 unsigned long len:1; /* Instruction length */ 626 unsigned long ec:6; /* Exception Class */ 627 } xabt; 628 629 #ifdef CONFIG_ARM_64 630 struct hsr_brk { 631 unsigned long comment:16; /* Comment */ 632 unsigned long res0:9; 633 unsigned long len:1; /* Instruction length */ 634 unsigned long ec:6; /* Exception Class */ 635 } brk; 636 #endif 637 638 639 }; 640 #endif 641 642 /* HSR.EC == HSR_CP{15,14,10}_32 */ 643 #define HSR_CP32_OP2_MASK (0x000e0000) 644 #define HSR_CP32_OP2_SHIFT (17) 645 #define HSR_CP32_OP1_MASK (0x0001c000) 646 #define HSR_CP32_OP1_SHIFT (14) 647 #define HSR_CP32_CRN_MASK (0x00003c00) 648 #define HSR_CP32_CRN_SHIFT (10) 649 #define HSR_CP32_CRM_MASK (0x0000001e) 650 #define HSR_CP32_CRM_SHIFT (1) 651 #define HSR_CP32_REGS_MASK (HSR_CP32_OP1_MASK|HSR_CP32_OP2_MASK|\ 652 HSR_CP32_CRN_MASK|HSR_CP32_CRM_MASK) 653 654 /* HSR.EC == HSR_CP{15,14}_64 */ 655 #define HSR_CP64_OP1_MASK (0x000f0000) 656 #define HSR_CP64_OP1_SHIFT (16) 657 #define HSR_CP64_CRM_MASK (0x0000001e) 658 #define HSR_CP64_CRM_SHIFT (1) 659 #define HSR_CP64_REGS_MASK (HSR_CP64_OP1_MASK|HSR_CP64_CRM_MASK) 660 661 /* HSR.EC == HSR_SYSREG */ 662 #define HSR_SYSREG_OP0_MASK (0x00300000) 663 #define HSR_SYSREG_OP0_SHIFT (20) 664 #define HSR_SYSREG_OP1_MASK (0x0001c000) 665 #define HSR_SYSREG_OP1_SHIFT (14) 666 #define HSR_SYSREG_CRN_MASK (0x00003c00) 667 #define HSR_SYSREG_CRN_SHIFT (10) 668 #define HSR_SYSREG_CRM_MASK (0x0000001e) 669 #define HSR_SYSREG_CRM_SHIFT (1) 670 #define HSR_SYSREG_OP2_MASK (0x000e0000) 671 #define HSR_SYSREG_OP2_SHIFT (17) 672 #define HSR_SYSREG_REGS_MASK (HSR_SYSREG_OP0_MASK|HSR_SYSREG_OP1_MASK|\ 673 HSR_SYSREG_CRN_MASK|HSR_SYSREG_CRM_MASK|\ 674 HSR_SYSREG_OP2_MASK) 675 676 /* HSR.EC == HSR_{HVC32, HVC64, SMC64, SVC32, SVC64} */ 677 #define HSR_XXC_IMM_MASK (0xffff) 678 679 /* Physical Address Register */ 680 #define PAR_F (_AC(1,U)<<0) 681 682 /* .... If F == 1 */ 683 #define PAR_FSC_SHIFT (1) 684 #define PAR_FSC_MASK (_AC(0x3f,U)<<PAR_FSC_SHIFT) 685 #define PAR_STAGE21 (_AC(1,U)<<8) /* Stage 2 Fault During Stage 1 Walk */ 686 #define PAR_STAGE2 (_AC(1,U)<<9) /* Stage 2 Fault */ 687 688 /* If F == 0 */ 689 #define PAR_MAIR_SHIFT 56 /* Memory Attributes */ 690 #define PAR_MAIR_MASK (0xffLL<<PAR_MAIR_SHIFT) 691 #define PAR_NS (_AC(1,U)<<9) /* Non-Secure */ 692 #define PAR_SH_SHIFT 7 /* Shareability */ 693 #define PAR_SH_MASK (_AC(3,U)<<PAR_SH_SHIFT) 694 695 /* Fault Status Register */ 696 /* 697 * 543210 BIT 698 * 00XXLL -- XX Fault Level LL 699 * ..01LL -- Translation Fault LL 700 * ..10LL -- Access Fault LL 701 * ..11LL -- Permission Fault LL 702 * 01xxxx -- Abort/Parity 703 * 10xxxx -- Other 704 * 11xxxx -- Implementation Defined 705 */ 706 #define FSC_TYPE_MASK (_AC(0x3,U)<<4) 707 #define FSC_TYPE_FAULT (_AC(0x00,U)<<4) 708 #define FSC_TYPE_ABT (_AC(0x01,U)<<4) 709 #define FSC_TYPE_OTH (_AC(0x02,U)<<4) 710 #define FSC_TYPE_IMPL (_AC(0x03,U)<<4) 711 712 #define FSC_FLT_TRANS (0x04) 713 #define FSC_FLT_ACCESS (0x08) 714 #define FSC_FLT_PERM (0x0c) 715 #define FSC_SEA (0x10) /* Synchronous External Abort */ 716 #define FSC_SPE (0x18) /* Memory Access Synchronous Parity Error */ 717 #define FSC_APE (0x11) /* Memory Access Asynchronous Parity Error */ 718 #define FSC_SEATT (0x14) /* Sync. Ext. Abort Translation Table */ 719 #define FSC_SPETT (0x1c) /* Sync. Parity. Error Translation Table */ 720 #define FSC_AF (0x21) /* Alignment Fault */ 721 #define FSC_DE (0x22) /* Debug Event */ 722 #define FSC_LKD (0x34) /* Lockdown Abort */ 723 #define FSC_CPR (0x3a) /* Coprocossor Abort */ 724 725 #define FSC_LL_MASK (_AC(0x03,U)<<0) 726 727 /* HPFAR_EL2: Hypervisor IPA Fault Address Register */ 728 #ifdef CONFIG_ARM_64 729 #define HPFAR_MASK GENMASK(39, 4) 730 #else 731 #define HPFAR_MASK GENMASK(31, 4) 732 #endif 733 734 /* Time counter hypervisor control register */ 735 #define CNTHCTL_EL2_EL1PCTEN (1u<<0) /* Kernel/user access to physical counter */ 736 #define CNTHCTL_EL2_EL1PCEN (1u<<1) /* Kernel/user access to CNTP timer regs */ 737 738 /* Time counter kernel control register */ 739 #define CNTKCTL_EL1_EL0PCTEN (1u<<0) /* Expose phys counters to EL0 */ 740 #define CNTKCTL_EL1_EL0VCTEN (1u<<1) /* Expose virt counters to EL0 */ 741 #define CNTKCTL_EL1_EL0VTEN (1u<<8) /* Expose virt timer registers to EL0 */ 742 #define CNTKCTL_EL1_EL0PTEN (1u<<9) /* Expose phys timer registers to EL0 */ 743 744 /* Timer control registers */ 745 #define CNTx_CTL_ENABLE (1u<<0) /* Enable timer */ 746 #define CNTx_CTL_MASK (1u<<1) /* Mask IRQ */ 747 #define CNTx_CTL_PENDING (1u<<2) /* IRQ pending */ 748 749 /* Exception Vector offsets */ 750 /* ... ARM32 */ 751 #define VECTOR32_RST 0 752 #define VECTOR32_UND 4 753 #define VECTOR32_SVC 8 754 #define VECTOR32_PABT 12 755 #define VECTOR32_DABT 16 756 /* ... ARM64 */ 757 #define VECTOR64_CURRENT_SP0_BASE 0x000 758 #define VECTOR64_CURRENT_SPx_BASE 0x200 759 #define VECTOR64_LOWER64_BASE 0x400 760 #define VECTOR64_LOWER32_BASE 0x600 761 762 #define VECTOR64_SYNC_OFFSET 0x000 763 #define VECTOR64_IRQ_OFFSET 0x080 764 #define VECTOR64_FIQ_OFFSET 0x100 765 #define VECTOR64_ERROR_OFFSET 0x180 766 767 768 #if defined(CONFIG_ARM_32) 769 # include <asm/arm32/processor.h> 770 #elif defined(CONFIG_ARM_64) 771 # include <asm/arm64/processor.h> 772 #else 773 # error "unknown ARM variant" 774 #endif 775 776 #ifndef __ASSEMBLY__ 777 extern uint32_t hyp_traps_vector[]; 778 779 void init_traps(void); 780 781 void panic_PAR(uint64_t par); 782 783 void show_execution_state(struct cpu_user_regs *regs); 784 void show_registers(struct cpu_user_regs *regs); 785 //#define dump_execution_state() run_in_exception_handler(show_execution_state) 786 #define dump_execution_state() WARN() 787 788 #define cpu_relax() barrier() /* Could yield? */ 789 790 /* All a bit UP for the moment */ 791 #define cpu_to_core(_cpu) (0) 792 #define cpu_to_socket(_cpu) (0) 793 794 void noreturn do_unexpected_trap(const char *msg, struct cpu_user_regs *regs); 795 796 struct vcpu; 797 void vcpu_regs_hyp_to_user(const struct vcpu *vcpu, 798 struct vcpu_guest_core_regs *regs); 799 void vcpu_regs_user_to_hyp(struct vcpu *vcpu, 800 const struct vcpu_guest_core_regs *regs); 801 802 int call_smc(register_t function_id, register_t arg0, register_t arg1, 803 register_t arg2); 804 805 void do_trap_hyp_serror(struct cpu_user_regs *regs); 806 807 void do_trap_guest_serror(struct cpu_user_regs *regs); 808 809 register_t get_default_hcr_flags(void); 810 811 /* Functions for pending virtual abort checking window. */ 812 void abort_guest_exit_start(void); 813 void abort_guest_exit_end(void); 814 815 #define VABORT_GEN_BY_GUEST(r) \ 816 ( \ 817 ( (unsigned long)abort_guest_exit_start == (r)->pc ) || \ 818 ( (unsigned long)abort_guest_exit_end == (r)->pc ) \ 819 ) 820 821 /* 822 * Synchronize SError unless the feature is selected. 823 * This is relying on the SErrors are currently unmasked. 824 */ 825 #define SYNCHRONIZE_SERROR(feat) \ 826 do { \ 827 ASSERT(!cpus_have_cap(feat) || local_abort_is_enabled()); \ 828 asm volatile(ALTERNATIVE("dsb sy; isb", \ 829 "nop; nop", feat) \ 830 : : : "memory"); \ 831 } while (0) 832 833 #endif /* __ASSEMBLY__ */ 834 #endif /* __ASM_ARM_PROCESSOR_H */ 835 /* 836 * Local variables: 837 * mode: C 838 * c-file-style: "BSD" 839 * c-basic-offset: 4 840 * indent-tabs-mode: nil 841 * End: 842 */ 843