1 #ifndef __XEN_X86_DEFNS_H__ 2 #define __XEN_X86_DEFNS_H__ 3 4 /* 5 * EFLAGS bits 6 */ 7 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ 8 #define X86_EFLAGS_MBS 0x00000002 /* Resvd bit */ 9 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ 10 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ 11 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ 12 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ 13 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ 14 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ 15 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ 16 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ 17 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ 18 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */ 19 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ 20 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ 21 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ 22 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ 23 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ 24 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ 25 26 #define X86_EFLAGS_ARITH_MASK \ 27 (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 28 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 29 30 /* 31 * Intel CPU flags in CR0 32 */ 33 #define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */ 34 #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */ 35 #define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */ 36 #define X86_CR0_TS 0x00000008 /* Task Switched (RW) */ 37 #define X86_CR0_ET 0x00000010 /* Extension type (RO) */ 38 #define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */ 39 #define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */ 40 #define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */ 41 #define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */ 42 #define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */ 43 #define X86_CR0_PG 0x80000000 /* Paging (RW) */ 44 45 /* 46 * Intel CPU features in CR4 47 */ 48 #define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ 49 #define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ 50 #define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ 51 #define X86_CR4_DE 0x00000008 /* enable debugging extensions */ 52 #define X86_CR4_PSE 0x00000010 /* enable page size extensions */ 53 #define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ 54 #define X86_CR4_MCE 0x00000040 /* Machine check enable */ 55 #define X86_CR4_PGE 0x00000080 /* enable global pages */ 56 #define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ 57 #define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ 58 #define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 59 #define X86_CR4_UMIP 0x00000800 /* enable UMIP */ 60 #define X86_CR4_VMXE 0x00002000 /* enable VMX */ 61 #define X86_CR4_SMXE 0x00004000 /* enable SMX */ 62 #define X86_CR4_FSGSBASE 0x00010000 /* enable {rd,wr}{fs,gs}base */ 63 #define X86_CR4_PCIDE 0x00020000 /* enable PCID */ 64 #define X86_CR4_OSXSAVE 0x00040000 /* enable XSAVE/XRSTOR */ 65 #define X86_CR4_SMEP 0x00100000 /* enable SMEP */ 66 #define X86_CR4_SMAP 0x00200000 /* enable SMAP */ 67 #define X86_CR4_PKE 0x00400000 /* enable PKE */ 68 69 #endif /* __XEN_X86_DEFNS_H__ */ 70