1  #ifndef __ASM_ARM_CPREGS_H
2  #define __ASM_ARM_CPREGS_H
3  
4  #include <xen/stringify.h>
5  
6  /*
7   * AArch32 Co-processor registers.
8   *
9   * Note that AArch64 requires many of these definitions in order to
10   * support 32-bit guests.
11   */
12  
13  #define __HSR_CPREG_c0  0
14  #define __HSR_CPREG_c1  1
15  #define __HSR_CPREG_c2  2
16  #define __HSR_CPREG_c3  3
17  #define __HSR_CPREG_c4  4
18  #define __HSR_CPREG_c5  5
19  #define __HSR_CPREG_c6  6
20  #define __HSR_CPREG_c7  7
21  #define __HSR_CPREG_c8  8
22  #define __HSR_CPREG_c9  9
23  #define __HSR_CPREG_c10 10
24  #define __HSR_CPREG_c11 11
25  #define __HSR_CPREG_c12 12
26  #define __HSR_CPREG_c13 13
27  #define __HSR_CPREG_c14 14
28  #define __HSR_CPREG_c15 15
29  
30  #define __HSR_CPREG_0   0
31  #define __HSR_CPREG_1   1
32  #define __HSR_CPREG_2   2
33  #define __HSR_CPREG_3   3
34  #define __HSR_CPREG_4   4
35  #define __HSR_CPREG_5   5
36  #define __HSR_CPREG_6   6
37  #define __HSR_CPREG_7   7
38  
39  #define _HSR_CPREG32(cp,op1,crn,crm,op2) \
40      ((__HSR_CPREG_##crn) << HSR_CP32_CRN_SHIFT) | \
41      ((__HSR_CPREG_##crm) << HSR_CP32_CRM_SHIFT) | \
42      ((__HSR_CPREG_##op1) << HSR_CP32_OP1_SHIFT) | \
43      ((__HSR_CPREG_##op2) << HSR_CP32_OP2_SHIFT)
44  
45  #define _HSR_CPREG64(cp,op1,crm) \
46      ((__HSR_CPREG_##crm) << HSR_CP64_CRM_SHIFT) | \
47      ((__HSR_CPREG_##op1) << HSR_CP64_OP1_SHIFT)
48  
49  /* Encode a register as per HSR ISS pattern */
50  #define HSR_CPREG32(X) _HSR_CPREG32(X)
51  #define HSR_CPREG64(X) _HSR_CPREG64(X)
52  
53  /*
54   * Order registers by Coprocessor-> CRn-> Opcode 1-> CRm-> Opcode 2
55   *
56   * This matches the ordering used in the ARM as well as the groupings
57   * which the CP registers are allocated in.
58   *
59   * This is slightly different to the form of the instruction
60   * arguments, which are cp,opc1,crn,crm,opc2.
61   */
62  
63  /* Coprocessor 10 */
64  
65  #define FPSID           p10,7,c0,c0,0   /* Floating-Point System ID Register */
66  #define FPSCR           p10,7,c1,c0,0   /* Floating-Point Status and Control Register */
67  #define MVFR0           p10,7,c7,c0,0   /* Media and VFP Feature Register 0 */
68  #define FPEXC           p10,7,c8,c0,0   /* Floating-Point Exception Control Register */
69  #define FPINST          p10,7,c9,c0,0   /* Floating-Point Instruction Register */
70  #define FPINST2         p10,7,c10,c0,0  /* Floating-point Instruction Register 2 */
71  
72  /* Coprocessor 14 */
73  
74  /* CP14 0: Debug Register interface */
75  #define DBGDIDR         p14,0,c0,c0,0   /* Debug ID Register */
76  #define DBGDSCRINT      p14,0,c0,c1,0   /* Debug Status and Control Internal */
77  #define DBGDSCREXT      p14,0,c0,c2,2   /* Debug Status and Control External */
78  #define DBGVCR          p14,0,c0,c7,0   /* Vector Catch */
79  #define DBGBVR0         p14,0,c0,c0,4   /* Breakpoint Value 0 */
80  #define DBGBCR0         p14,0,c0,c0,5   /* Breakpoint Control 0 */
81  #define DBGWVR0         p14,0,c0,c0,6   /* Watchpoint Value 0 */
82  #define DBGWCR0         p14,0,c0,c0,7   /* Watchpoint Control 0 */
83  #define DBGBVR1         p14,0,c0,c1,4   /* Breakpoint Value 1 */
84  #define DBGBCR1         p14,0,c0,c1,5   /* Breakpoint Control 1 */
85  #define DBGOSLAR        p14,0,c1,c0,4   /* OS Lock Access */
86  #define DBGOSLSR        p14,0,c1,c1,4   /* OS Lock Status Register */
87  #define DBGOSDLR        p14,0,c1,c3,4   /* OS Double Lock */
88  #define DBGPRCR         p14,0,c1,c4,4   /* Debug Power Control Register */
89  
90  /* CP14 CR0: */
91  #define TEECR           p14,6,c0,c0,0   /* ThumbEE Configuration Register */
92  
93  /* CP14 CR1: */
94  #define DBGDRAR64       p14,0,c1        /* Debug ROM Address Register (64-bit access) */
95  #define DBGDRAR         p14,0,c1,c0,0   /* Debug ROM Address Register (32-bit access) */
96  #define TEEHBR          p14,6,c1,c0,0   /* ThumbEE Handler Base Register */
97  #define JOSCR           p14,7,c1,c0,0   /* Jazelle OS Control Register */
98  
99  /* CP14 CR2: */
100  #define DBGDSAR64       p14,0,c2        /* Debug Self Address Offset Register (64-bit access) */
101  #define DBGDSAR         p14,0,c2,c0,0   /* Debug Self Address Offset Register (32-bit access) */
102  #define JMCR            p14,7,c2,c0,0   /* Jazelle Main Configuration Register */
103  
104  
105  /* Coprocessor 15 */
106  
107  /* CP15 CR0: CPUID and Cache Type Registers */
108  #define MIDR            p15,0,c0,c0,0   /* Main ID Register */
109  #define MPIDR           p15,0,c0,c0,5   /* Multiprocessor Affinity Register */
110  #define ID_PFR0         p15,0,c0,c1,0   /* Processor Feature Register 0 */
111  #define ID_PFR1         p15,0,c0,c1,1   /* Processor Feature Register 1 */
112  #define ID_DFR0         p15,0,c0,c1,2   /* Debug Feature Register 0 */
113  #define ID_AFR0         p15,0,c0,c1,3   /* Auxiliary Feature Register 0 */
114  #define ID_MMFR0        p15,0,c0,c1,4   /* Memory Model Feature Register 0 */
115  #define ID_MMFR1        p15,0,c0,c1,5   /* Memory Model Feature Register 1 */
116  #define ID_MMFR2        p15,0,c0,c1,6   /* Memory Model Feature Register 2 */
117  #define ID_MMFR3        p15,0,c0,c1,7   /* Memory Model Feature Register 3 */
118  #define ID_ISAR0        p15,0,c0,c2,0   /* ISA Feature Register 0 */
119  #define ID_ISAR1        p15,0,c0,c2,1   /* ISA Feature Register 1 */
120  #define ID_ISAR2        p15,0,c0,c2,2   /* ISA Feature Register 2 */
121  #define ID_ISAR3        p15,0,c0,c2,3   /* ISA Feature Register 3 */
122  #define ID_ISAR4        p15,0,c0,c2,4   /* ISA Feature Register 4 */
123  #define ID_ISAR5        p15,0,c0,c2,5   /* ISA Feature Register 5 */
124  #define CCSIDR          p15,1,c0,c0,0   /* Cache Size ID Registers */
125  #define CLIDR           p15,1,c0,c0,1   /* Cache Level ID Register */
126  #define CSSELR          p15,2,c0,c0,0   /* Cache Size Selection Register */
127  #define VPIDR           p15,4,c0,c0,0   /* Virtualization Processor ID Register */
128  #define VMPIDR          p15,4,c0,c0,5   /* Virtualization Multiprocessor ID Register */
129  
130  /* CP15 CR1: System Control Registers */
131  #define SCTLR           p15,0,c1,c0,0   /* System Control Register */
132  #define ACTLR           p15,0,c1,c0,1   /* Auxiliary Control Register */
133  #define CPACR           p15,0,c1,c0,2   /* Coprocessor Access Control Register */
134  #define SCR             p15,0,c1,c1,0   /* Secure Configuration Register */
135  #define NSACR           p15,0,c1,c1,2   /* Non-Secure Access Control Register */
136  #define HSCTLR          p15,4,c1,c0,0   /* Hyp. System Control Register */
137  #define HCR             p15,4,c1,c1,0   /* Hyp. Configuration Register */
138  #define HDCR            p15,4,c1,c1,1   /* Hyp. Debug Configuration Register */
139  #define HCPTR           p15,4,c1,c1,2   /* Hyp. Coprocessor Trap Register */
140  #define HSTR            p15,4,c1,c1,3   /* Hyp. System Trap Register */
141  
142  /* CP15 CR2: Translation Table Base and Control Registers */
143  #define TTBCR           p15,0,c2,c0,2   /* Translatation Table Base Control Register */
144  #define TTBR0           p15,0,c2        /* Translation Table Base Reg. 0 */
145  #define TTBR1           p15,1,c2        /* Translation Table Base Reg. 1 */
146  #define HTTBR           p15,4,c2        /* Hyp. Translation Table Base Register */
147  #define TTBR0_32        p15,0,c2,c0,0   /* 32-bit access to TTBR0 */
148  #define TTBR1_32        p15,0,c2,c0,1   /* 32-bit access to TTBR1 */
149  #define HTCR            p15,4,c2,c0,2   /* Hyp. Translation Control Register */
150  #define VTCR            p15,4,c2,c1,2   /* Virtualization Translation Control Register */
151  #define VTTBR           p15,6,c2        /* Virtualization Translation Table Base Register */
152  
153  /* CP15 CR3: Domain Access Control Register */
154  #define DACR            p15,0,c3,c0,0   /* Domain Access Control Register */
155  
156  /* CP15 CR4: */
157  
158  /* CP15 CR5: Fault Status Registers */
159  #define DFSR            p15,0,c5,c0,0   /* Data Fault Status Register */
160  #define IFSR            p15,0,c5,c0,1   /* Instruction Fault Status Register */
161  #define ADFSR           p15,0,c5,c1,0   /* Auxiliary Data Fault Status Register */
162  #define AIFSR           p15,0,c5,c1,1   /* Auxiliary Instruction Fault Status Register */
163  #define HSR             p15,4,c5,c2,0   /* Hyp. Syndrome Register */
164  
165  /* CP15 CR6: Fault Address Registers */
166  #define DFAR            p15,0,c6,c0,0   /* Data Fault Address Register  */
167  #define IFAR            p15,0,c6,c0,2   /* Instruction Fault Address Register */
168  #define HDFAR           p15,4,c6,c0,0   /* Hyp. Data Fault Address Register */
169  #define HIFAR           p15,4,c6,c0,2   /* Hyp. Instruction Fault Address Register */
170  #define HPFAR           p15,4,c6,c0,4   /* Hyp. IPA Fault Address Register */
171  
172  /* CP15 CR7: Cache and address translation operations */
173  #define PAR             p15,0,c7        /* Physical Address Register */
174  
175  #define ICIALLUIS       p15,0,c7,c1,0   /* Invalidate all instruction caches to PoU inner shareable */
176  #define BPIALLIS        p15,0,c7,c1,6   /* Invalidate entire branch predictor array inner shareable */
177  #define ICIALLU         p15,0,c7,c5,0   /* Invalidate all instruction caches to PoU */
178  #define ICIMVAU         p15,0,c7,c5,1   /* Invalidate instruction caches by MVA to PoU */
179  #define BPIALL          p15,0,c7,c5,6   /* Invalidate entire branch predictor array */
180  #define BPIMVA          p15,0,c7,c5,7   /* Invalidate MVA from branch predictor array */
181  #define DCIMVAC         p15,0,c7,c6,1   /* Invalidate data cache line by MVA to PoC */
182  #define DCISW           p15,0,c7,c6,2   /* Invalidate data cache line by set/way */
183  #define ATS1CPR         p15,0,c7,c8,0   /* Address Translation Stage 1. Non-Secure Kernel Read */
184  #define ATS1CPW         p15,0,c7,c8,1   /* Address Translation Stage 1. Non-Secure Kernel Write */
185  #define ATS1CUR         p15,0,c7,c8,2   /* Address Translation Stage 1. Non-Secure User Read */
186  #define ATS1CUW         p15,0,c7,c8,3   /* Address Translation Stage 1. Non-Secure User Write */
187  #define ATS12NSOPR      p15,0,c7,c8,4   /* Address Translation Stage 1+2 Non-Secure Kernel Read */
188  #define ATS12NSOPW      p15,0,c7,c8,5   /* Address Translation Stage 1+2 Non-Secure Kernel Write */
189  #define ATS12NSOUR      p15,0,c7,c8,6   /* Address Translation Stage 1+2 Non-Secure User Read */
190  #define ATS12NSOUW      p15,0,c7,c8,7   /* Address Translation Stage 1+2 Non-Secure User Write */
191  #define DCCMVAC         p15,0,c7,c10,1  /* Clean data or unified cache line by MVA to PoC */
192  #define DCCSW           p15,0,c7,c10,2  /* Clean data cache line by set/way */
193  #define DCCMVAU         p15,0,c7,c11,1  /* Clean data cache line by MVA to PoU */
194  #define DCCIMVAC        p15,0,c7,c14,1  /* Data cache clean and invalidate by MVA */
195  #define DCCISW          p15,0,c7,c14,2  /* Clean and invalidate data cache line by set/way */
196  #define ATS1HR          p15,4,c7,c8,0   /* Address Translation Stage 1 Hyp. Read */
197  #define ATS1HW          p15,4,c7,c8,1   /* Address Translation Stage 1 Hyp. Write */
198  
199  /* CP15 CR8: TLB maintenance operations */
200  #define TLBIALLIS       p15,0,c8,c3,0   /* Invalidate entire TLB innrer shareable */
201  #define TLBIMVAIS       p15,0,c8,c3,1   /* Invalidate unified TLB entry by MVA inner shareable */
202  #define TLBIASIDIS      p15,0,c8,c3,2   /* Invalidate unified TLB by ASID match inner shareable */
203  #define TLBIMVAAIS      p15,0,c8,c3,3   /* Invalidate unified TLB entry by MVA all ASID inner shareable */
204  #define ITLBIALL        p15,0,c8,c5,0   /* Invalidate instruction TLB */
205  #define ITLBIMVA        p15,0,c8,c5,1   /* Invalidate instruction TLB entry by MVA */
206  #define ITLBIASID       p15,0,c8,c5,2   /* Invalidate instruction TLB by ASID match */
207  #define DTLBIALL        p15,0,c8,c6,0   /* Invalidate data TLB */
208  #define DTLBIMVA        p15,0,c8,c6,1   /* Invalidate data TLB entry by MVA */
209  #define DTLBIASID       p15,0,c8,c6,2   /* Invalidate data TLB by ASID match */
210  #define TLBIALL         p15,0,c8,c7,0   /* invalidate unified TLB */
211  #define TLBIMVA         p15,0,c8,c7,1   /* invalidate unified TLB entry by MVA */
212  #define TLBIASID        p15,0,c8,c7,2   /* invalid unified TLB by ASID match */
213  #define TLBIMVAA        p15,0,c8,c7,3   /* invalidate unified TLB entries by MVA all ASID */
214  #define TLBIALLHIS      p15,4,c8,c3,0   /* Invalidate Entire Hyp. Unified TLB inner shareable */
215  #define TLBIMVAHIS      p15,4,c8,c3,1   /* Invalidate Unified Hyp. TLB by MVA inner shareable */
216  #define TLBIALLNSNHIS   p15,4,c8,c3,4   /* Invalidate Entire Non-Secure Non-Hyp. Unified TLB inner shareable */
217  #define TLBIALLH        p15,4,c8,c7,0   /* Invalidate Entire Hyp. Unified TLB */
218  #define TLBIMVAH        p15,4,c8,c7,1   /* Invalidate Unified Hyp. TLB by MVA */
219  #define TLBIALLNSNH     p15,4,c8,c7,4   /* Invalidate Entire Non-Secure Non-Hyp. Unified TLB */
220  
221  /* CP15 CR9: Performance monitors */
222  #define PMCR            p15,0,c9,c12,0  /* Perf. Mon. Control Register */
223  #define PMCNTENSET      p15,0,c9,c12,1  /* Perf. Mon. Count Enable Set register */
224  #define PMCNTENCLR      p15,0,c9,c12,2  /* Perf. Mon. Count Enable Clear register */
225  #define PMOVSR          p15,0,c9,c12,3  /* Perf. Mon. Overflow Flag Status Register */
226  #define PMSWINC         p15,0,c9,c12,4  /* Perf. Mon. Software Increment register */
227  #define PMSELR          p15,0,c9,c12,5  /* Perf. Mon. Event Counter Selection Register */
228  #define PMCEID0         p15,0,c9,c12,6  /* Perf. Mon. Common Event Identification register 0 */
229  #define PMCEID1         p15,0,c9,c12,7  /* Perf. Mon. Common Event Identification register 1 */
230  #define PMCCNTR         p15,0,c9,c13,0  /* Perf. Mon. Cycle Count Register */
231  #define PMXEVTYPER      p15,0,c9,c13,1  /* Perf. Mon. Event Type Select Register */
232  #define PMXEVCNTR       p15,0,c9,c13,2  /* Perf. Mon. Event Count Register */
233  #define PMUSERENR       p15,0,c9,c14,0  /* Perf. Mon. User Enable Register */
234  #define PMINTENSET      p15,0,c9,c14,1  /* Perf. Mon. Interrupt Enable Set Register */
235  #define PMINTENCLR      p15,0,c9,c14,2  /* Perf. Mon. Interrupt Enable Clear Register */
236  #define PMOVSSET        p15,0,c9,c14,3  /* Perf. Mon. Overflow Flag Status Set register */
237  
238  /* CP15 CR10: */
239  #define MAIR0           p15,0,c10,c2,0  /* Memory Attribute Indirection Register 0 AKA PRRR */
240  #define MAIR1           p15,0,c10,c2,1  /* Memory Attribute Indirection Register 1 AKA NMRR */
241  #define HMAIR0          p15,4,c10,c2,0  /* Hyp. Memory Attribute Indirection Register 0 */
242  #define HMAIR1          p15,4,c10,c2,1  /* Hyp. Memory Attribute Indirection Register 1 */
243  #define AMAIR0          p15,0,c10,c3,0  /* Aux. Memory Attribute Indirection Register 0 */
244  #define AMAIR1          p15,0,c10,c3,1  /* Aux. Memory Attribute Indirection Register 1 */
245  
246  /* CP15 CR11: DMA Operations for TCM Access */
247  
248  /* CP15 CR12:  */
249  #define ICC_SGI1R       p15,0,c12       /* Interrupt Controller SGI Group 1 */
250  #define ICC_ASGI1R      p15,1,c12       /* Interrupt Controller Alias SGI Group 1 Register */
251  #define ICC_SGI0R       p15,2,c12       /* Interrupt Controller SGI Group 0 */
252  #define VBAR            p15,0,c12,c0,0  /* Vector Base Address Register */
253  #define HVBAR           p15,4,c12,c0,0  /* Hyp. Vector Base Address Register */
254  
255  /* CP15 CR13:  */
256  #define FCSEIDR         p15,0,c13,c0,0  /* FCSE Process ID Register */
257  #define CONTEXTIDR      p15,0,c13,c0,1  /* Context ID Register */
258  #define TPIDRURW        p15,0,c13,c0,2  /* Software Thread ID, User, R/W */
259  #define TPIDRURO        p15,0,c13,c0,3  /* Software Thread ID, User, R/O */
260  #define TPIDRPRW        p15,0,c13,c0,4  /* Software Thread ID, Priveleged */
261  #define HTPIDR          p15,4,c13,c0,2  /* HYp Software Thread Id Register */
262  
263  /* CP15 CR14:  */
264  #define CNTPCT          p15,0,c14       /* Time counter value */
265  #define CNTFRQ          p15,0,c14,c0,0  /* Time counter frequency */
266  #define CNTKCTL         p15,0,c14,c1,0  /* Time counter kernel control */
267  #define CNTP_TVAL       p15,0,c14,c2,0  /* Physical Timer value */
268  #define CNTP_CTL        p15,0,c14,c2,1  /* Physical Timer control register */
269  #define CNTVCT          p15,1,c14       /* Time counter value + offset */
270  #define CNTP_CVAL       p15,2,c14       /* Physical Timer comparator */
271  #define CNTV_CVAL       p15,3,c14       /* Virt. Timer comparator */
272  #define CNTVOFF         p15,4,c14       /* Time counter offset */
273  #define CNTHCTL         p15,4,c14,c1,0  /* Time counter hyp. control */
274  #define CNTHP_TVAL      p15,4,c14,c2,0  /* Hyp. Timer value */
275  #define CNTHP_CTL       p15,4,c14,c2,1  /* Hyp. Timer control register */
276  #define CNTV_TVAL       p15,0,c14,c3,0  /* Virt. Timer value */
277  #define CNTV_CTL        p15,0,c14,c3,1  /* Virt. TImer control register */
278  #define CNTHP_CVAL      p15,6,c14       /* Hyp. Timer comparator */
279  
280  /* CP15 CR15: Implementation Defined Registers */
281  
282  /* Aliases of AArch64 names for use in common code when building for AArch32 */
283  #ifdef CONFIG_ARM_32
284  /* Alphabetically... */
285  #define ACTLR_EL1               ACTLR
286  #define AFSR0_EL1               ADFSR
287  #define AFSR1_EL1               AIFSR
288  #define CCSIDR_EL1              CCSIDR
289  #define CLIDR_EL1               CLIDR
290  #define CNTFRQ_EL0              CNTFRQ
291  #define CNTHCTL_EL2             CNTHCTL
292  #define CNTHP_CTL_EL2           CNTHP_CTL
293  #define CNTHP_CVAL_EL2          CNTHP_CVAL
294  #define CNTKCTL_EL1             CNTKCTL
295  #define CNTPCT_EL0              CNTPCT
296  #define CNTP_CTL_EL0            CNTP_CTL
297  #define CNTP_CVAL_EL0           CNTP_CVAL
298  #define CNTVCT_EL0              CNTVCT
299  #define CNTVOFF_EL2             CNTVOFF
300  #define CNTV_CTL_EL0            CNTV_CTL
301  #define CNTV_CVAL_EL0           CNTV_CVAL
302  #define CONTEXTIDR_EL1          CONTEXTIDR
303  #define CPACR_EL1               CPACR
304  #define CPTR_EL2                HCPTR
305  #define CSSELR_EL1              CSSELR
306  #define DACR32_EL2              DACR
307  #define ESR_EL1                 DFSR
308  #define ESR_EL2                 HSR
309  #define HCR_EL2                 HCR
310  #define HPFAR_EL2               HPFAR
311  #define HSTR_EL2                HSTR
312  #define ID_AFR0_EL1             ID_AFR0
313  #define ID_DFR0_EL1             ID_DFR0
314  #define ID_ISAR0_EL1            ID_ISAR0
315  #define ID_ISAR1_EL1            ID_ISAR1
316  #define ID_ISAR2_EL1            ID_ISAR2
317  #define ID_ISAR3_EL1            ID_ISAR3
318  #define ID_ISAR4_EL1            ID_ISAR4
319  #define ID_ISAR5_EL1            ID_ISAR5
320  #define ID_MMFR0_EL1            ID_MMFR0
321  #define ID_MMFR1_EL1            ID_MMFR1
322  #define ID_MMFR2_EL1            ID_MMFR2
323  #define ID_MMFR3_EL1            ID_MMFR3
324  #define ID_PFR0_EL1             ID_PFR0
325  #define ID_PFR1_EL1             ID_PFR1
326  #define IFSR32_EL2              IFSR
327  #define MDCR_EL2                HDCR
328  #define MIDR_EL1                MIDR
329  #define MPIDR_EL1               MPIDR
330  #define PAR_EL1                 PAR
331  #define SCTLR_EL1               SCTLR
332  #define SCTLR_EL2               HSCTLR
333  #define TCR_EL1                 TTBCR
334  #define TEECR32_EL1             TEECR
335  #define TEEHBR32_EL1            TEEHBR
336  #define TPIDRRO_EL0             TPIDRURO
337  #define TPIDR_EL0               TPIDRURW
338  #define TPIDR_EL1               TPIDRPRW
339  #define TPIDR_EL2               HTPIDR
340  #define TTBR0_EL1               TTBR0
341  #define TTBR0_EL2               HTTBR
342  #define TTBR1_EL1               TTBR1
343  #define VBAR_EL1                VBAR
344  #define VBAR_EL2                HVBAR
345  #define VMPIDR_EL2              VMPIDR
346  #define VPIDR_EL2               VPIDR
347  #define VTCR_EL2                VTCR
348  #define VTTBR_EL2               VTTBR
349  #endif
350  
351  #endif
352  /*
353   * Local variables:
354   * mode: C
355   * c-file-style: "BSD"
356   * c-basic-offset: 4
357   * indent-tabs-mode: nil
358   * End:
359   */
360