Searched refs:counter_config (Results 1 – 6 of 6) sorted by relevance
| /xen-4.10.0-shim-comet/xen/arch/x86/oprofile/ |
| A D | xenoprof.c | 30 counter_config[counter.ind].count = counter.count; in xenoprof_arch_counter()
31 counter_config[counter.ind].enabled = counter.enabled; in xenoprof_arch_counter()
32 counter_config[counter.ind].event = counter.event; in xenoprof_arch_counter()
33 counter_config[counter.ind].kernel = counter.kernel; in xenoprof_arch_counter()
34 counter_config[counter.ind].user = counter.user; in xenoprof_arch_counter()
35 counter_config[counter.ind].unit_mask = counter.unit_mask; in xenoprof_arch_counter()
67 counter_config[counter.ind].count = counter.count; in compat_oprof_arch_counter()
68 counter_config[counter.ind].enabled = counter.enabled; in compat_oprof_arch_counter()
69 counter_config[counter.ind].event = counter.event; in compat_oprof_arch_counter()
70 counter_config[counter.ind].kernel = counter.kernel; in compat_oprof_arch_counter()
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| A D | op_model_p4.c | 487 if (counter_config[ctr].event <= 0 || counter_config[ctr].event > NUM_EVENTS) { in pmc_setup_one_p4_counter()
489 counter_config[ctr].event); in pmc_setup_one_p4_counter()
493 ev = &(p4_events[counter_config[ctr].event - 1]); in pmc_setup_one_p4_counter()
502 ESCR_SET_USR_0(escr, counter_config[ctr].user); in pmc_setup_one_p4_counter()
503 ESCR_SET_OS_0(escr, counter_config[ctr].kernel); in pmc_setup_one_p4_counter()
505 ESCR_SET_USR_1(escr, counter_config[ctr].user); in pmc_setup_one_p4_counter()
506 ESCR_SET_OS_1(escr, counter_config[ctr].kernel); in pmc_setup_one_p4_counter()
529 counter_config[ctr].event, stag, ctr); in pmc_setup_one_p4_counter()
602 if (counter_config[i].enabled) { in p4_setup_ctrs()
603 reset_value[i] = counter_config[i].count; in p4_setup_ctrs()
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| A D | op_model_ppro.c | 112 if (counter_config[i].enabled) { in ppro_setup_ctrs()
113 reset_value[i] = counter_config[i].count; in ppro_setup_ctrs()
120 CTRL_SET_USR(msr_content, counter_config[i].user); in ppro_setup_ctrs()
121 CTRL_SET_KERN(msr_content, counter_config[i].kernel); in ppro_setup_ctrs()
122 CTRL_SET_UM(msr_content, counter_config[i].unit_mask); in ppro_setup_ctrs()
123 CTRL_SET_EVENT(msr_content, counter_config[i].event); in ppro_setup_ctrs()
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| A D | op_model_athlon.c | 218 if (counter_config[i].enabled) { in athlon_setup_ctrs()
219 reset_value[i] = counter_config[i].count; in athlon_setup_ctrs()
221 CTR_WRITE(counter_config[i].count, msrs, i); in athlon_setup_ctrs()
226 CTRL_SET_USR(msr_content, counter_config[i].user); in athlon_setup_ctrs()
227 CTRL_SET_KERN(msr_content, counter_config[i].kernel); in athlon_setup_ctrs()
228 CTRL_SET_UM(msr_content, counter_config[i].unit_mask); in athlon_setup_ctrs()
229 CTRL_SET_EVENT(msr_content, counter_config[i].event); in athlon_setup_ctrs()
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| A D | op_counter.h | 27 extern struct op_counter_config counter_config[];
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| A D | nmi_int.c | 31 struct op_counter_config counter_config[OP_MAX_COUNTER]; variable
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