Searched refs:cpsr (Results 1 – 20 of 20) sorted by relevance
| /xen-4.10.0-shim-comet/xen/include/asm-arm/ |
| A D | regs.h | 16 #define usr_mode(r) psr_mode((r)->cpsr,PSR_MODE_USR)
17 #define fiq_mode(r) psr_mode((r)->cpsr,PSR_MODE_FIQ)
18 #define irq_mode(r) psr_mode((r)->cpsr,PSR_MODE_IRQ)
19 #define svc_mode(r) psr_mode((r)->cpsr,PSR_MODE_SVC)
20 #define mon_mode(r) psr_mode((r)->cpsr,PSR_MODE_MON)
21 #define abt_mode(r) psr_mode((r)->cpsr,PSR_MODE_ABT)
22 #define und_mode(r) psr_mode((r)->cpsr,PSR_MODE_UND)
23 #define sys_mode(r) psr_mode((r)->cpsr,PSR_MODE_SYS)
26 #define hyp_mode(r) psr_mode((r)->cpsr,PSR_MODE_HYP)
30 psr_mode((r)->cpsr,PSR_MODE_EL2t))
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| A D | event.h | 14 return !(regs->cpsr & PSR_IRQ_MASK); in vcpu_event_delivery_is_enabled()
53 regs->cpsr &= ~PSR_IRQ_MASK; in local_event_delivery_enable()
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| /xen-4.10.0-shim-comet/xen/arch/arm/ |
| A D | traps.c | 411 regs->cpsr |= mode; in cpsr_switch_mode()
412 regs->cpsr |= PSR_IRQ_MASK; in cpsr_switch_mode()
1632 cpsr = regs->cpsr; in check_conditional_instr()
1639 BUG_ON( !psr_mode_is_32bit(regs->cpsr) || !(cpsr&PSR_THUMB) ); in check_conditional_instr()
1641 it = ( (cpsr >> (10-2)) & 0xfc) | ((cpsr >> 25) & 0x3 ); in check_conditional_instr()
1651 cpsr_cond = cpsr >> 28; in check_conditional_instr()
1663 unsigned long itbits, cond, cpsr = regs->cpsr; in advance_pc() local
1666 BUG_ON( (!psr_mode_is_32bit(cpsr)||!(cpsr&PSR_THUMB)) in advance_pc()
1669 if ( cpsr&PSR_IT_MASK ) in advance_pc()
1691 cpsr |= cond << 13; in advance_pc()
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| A D | vm_event.c | 28 req->data.regs.arm.cpsr = regs->cpsr; in vm_event_fill_regs()
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| A D | vpsci.c | 61 ctxt->user_regs.cpsr = PSR_GUEST32_INIT; in do_common_cpu_on()
68 ctxt->user_regs.cpsr = PSR_GUEST64_INIT; in do_common_cpu_on()
76 ctxt->user_regs.cpsr |= PSR_THUMB; in do_common_cpu_on()
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| A D | decode.c | 154 if ( is_32bit_domain(current->domain) && regs->cpsr & PSR_THUMB ) in decode_instruction()
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| A D | domain.c | 772 if ( !is_guest_pv32_psr(regs->cpsr) ) in arch_set_info_guest()
789 if ( !is_guest_pv64_psr(regs->cpsr) ) in arch_set_info_guest()
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| A D | domain_build.c | 2206 regs->cpsr = PSR_GUEST32_INIT; in construct_dom0()
2225 regs->cpsr = PSR_GUEST64_INIT; in construct_dom0()
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| /xen-4.10.0-shim-comet/xen/arch/arm/arm32/ |
| A D | domain.c | 25 C(cpsr,cpsr)
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| A D | asm-offsets.c | 28 OFFSET(UREGS_cpsr, struct cpu_user_regs, cpsr); in __dummy__()
60 OFFSET(UREGS_kernel_sizeof, struct cpu_user_regs, cpsr); in __dummy__()
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| A D | head.S | 172 mrs r0, cpsr
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| /xen-4.10.0-shim-comet/xen/arch/arm/arm64/ |
| A D | domain.c | 19 C(cpsr, cpsr); C(spsr_el1, spsr_el1)
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| A D | asm-offsets.c | 29 OFFSET(UREGS_CPSR, struct cpu_user_regs, cpsr); in __dummy__()
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| /xen-4.10.0-shim-comet/tools/libxc/ |
| A D | xc_dom_arm.c | 157 ctxt->user_regs.cpsr = PSR_GUEST32_INIT; in vcpu_arm32()
162 ctxt->user_regs.cpsr, ctxt->user_regs.pc32); in vcpu_arm32()
199 ctxt->user_regs.cpsr = PSR_GUEST64_INIT; in vcpu_arm64()
204 ctxt->user_regs.cpsr, ctxt->user_regs.pc64); in vcpu_arm64()
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| /xen-4.10.0-shim-comet/xen/include/asm-arm/arm64/ |
| A D | processor.h | 70 uint32_t cpsr; /* SPSR_EL2 */ member
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| /xen-4.10.0-shim-comet/xen/include/asm-arm/arm32/ |
| A D | processor.h | 41 uint32_t cpsr; /* Return mode */ member
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| /xen-4.10.0-shim-comet/xen/include/public/ |
| A D | vm_event.h | 209 uint32_t cpsr; member
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| A D | arch-arm.h | 256 uint32_t cpsr; /* SPSR_EL2 */ member
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| /xen-4.10.0-shim-comet/xen/arch/arm/arm32/lib/ |
| A D | assembler.h | 145 mrs \oldcpsr, cpsr
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| /xen-4.10.0-shim-comet/tools/xentrace/ |
| A D | xenctx.c | 559 printf("CPSR: %08"PRIx32"\n", regs->cpsr); in print_ctx_32()
615 printf("CPSR: %08"PRIx32"\n", regs->cpsr); in print_ctx_64()
670 if (ctx->user_regs.cpsr & PSR_MODE_BIT) in print_ctx()
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