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Searched refs:midr (Results 1 – 5 of 5) sorted by relevance

/xen-4.10.0-shim-comet/xen/include/asm-arm/
A Dprocessor.h11 #define MIDR_RESIVION(midr) ((midr) & MIDR_REVISION_MASK) argument
14 #define MIDR_PARTNUM(midr) \ argument
15 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
18 #define MIDR_ARCHITECTURE(midr) \ argument
19 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
22 #define MIDR_VARIANT(midr) \ argument
23 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
26 #define MIDR_IMPLEMENTOR(midr) \ argument
27 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
37 #define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \ argument
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/xen-4.10.0-shim-comet/xen/arch/arm/
A Dsetup.c99 if ( c->midr.implementer < ARRAY_SIZE(processor_implementers) && in processor_id()
100 processor_implementers[c->midr.implementer] ) in processor_id()
101 implementer = processor_implementers[c->midr.implementer]; in processor_id()
103 if ( c->midr.architecture != 0xf ) in processor_id()
105 c->midr.architecture); in processor_id()
108 c->midr.bits, implementer, in processor_id()
109 c->midr.variant, c->midr.part_number, c->midr.revision); in processor_id()
A Dcpuerrata.c13 return MIDR_IS_CPU_MODEL_RANGE(boot_cpu_data.midr.bits, entry->midr_model, in is_affected_midr_range()
A Dcpu.c21 c->midr.bits = READ_SYSREG32(MIDR_EL1); in identify_cpu()
A Ddomain.c600 d->arch.vpidr = boot_cpu_data.midr.bits; in arch_domain_create()

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