1 #ifndef __ASM_MSI_H 2 #define __ASM_MSI_H 3 4 #include <xen/cpumask.h> 5 #include <xen/pci.h> 6 #include <asm/byteorder.h> 7 #include <asm/hvm/vmx/vmcs.h> 8 9 /* 10 * Constants for Intel APIC based MSI messages. 11 */ 12 13 /* 14 * Shifts for MSI data 15 */ 16 17 #define MSI_DATA_VECTOR_SHIFT 0 18 #define MSI_DATA_VECTOR_MASK 0x000000ff 19 #define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & MSI_DATA_VECTOR_MASK) 20 21 #define MSI_DATA_DELIVERY_MODE_SHIFT 8 22 #define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT) 23 #define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT) 24 #define MSI_DATA_DELIVERY_MODE_MASK 0x00000700 25 26 #define MSI_DATA_LEVEL_SHIFT 14 27 #define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT) 28 #define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT) 29 30 #define MSI_DATA_TRIGGER_SHIFT 15 31 #define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT) 32 #define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT) 33 #define MSI_DATA_TRIGGER_MASK 0x00008000 34 35 /* 36 * Shift/mask fields for msi address 37 */ 38 39 #define MSI_ADDR_BASE_HI 0 40 #define MSI_ADDR_BASE_LO 0xfee00000 41 #define MSI_ADDR_HEADER MSI_ADDR_BASE_LO 42 43 #define MSI_ADDR_DESTMODE_SHIFT 2 44 #define MSI_ADDR_DESTMODE_PHYS (0 << MSI_ADDR_DESTMODE_SHIFT) 45 #define MSI_ADDR_DESTMODE_LOGIC (1 << MSI_ADDR_DESTMODE_SHIFT) 46 #define MSI_ADDR_DESTMODE_MASK 0x4 47 48 #define MSI_ADDR_REDIRECTION_SHIFT 3 49 #define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) 50 #define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) 51 52 #define MSI_ADDR_DEST_ID_SHIFT 12 53 #define MSI_ADDR_DEST_ID_MASK 0x00ff000 54 #define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & MSI_ADDR_DEST_ID_MASK) 55 56 /* MAX fixed pages reserved for mapping MSIX tables. */ 57 #define FIX_MSIX_MAX_PAGES 512 58 59 struct msi_info { 60 u16 seg; 61 u8 bus; 62 u8 devfn; 63 int irq; 64 int entry_nr; 65 uint64_t table_base; 66 }; 67 68 struct msi_msg { 69 union { 70 u64 address; /* message address */ 71 struct { 72 u32 address_lo; /* message address low 32 bits */ 73 u32 address_hi; /* message address high 32 bits */ 74 }; 75 }; 76 u32 data; /* 16 bits of msi message data */ 77 u32 dest32; /* used when Interrupt Remapping with EIM is enabled */ 78 }; 79 80 struct irq_desc; 81 struct hw_interrupt_type; 82 struct msi_desc; 83 /* Helper functions */ 84 extern int pci_enable_msi(struct msi_info *msi, struct msi_desc **desc); 85 extern void pci_disable_msi(struct msi_desc *desc); 86 extern int pci_prepare_msix(u16 seg, u8 bus, u8 devfn, bool off); 87 extern void pci_cleanup_msi(struct pci_dev *pdev); 88 extern int setup_msi_irq(struct irq_desc *, struct msi_desc *); 89 extern int __setup_msi_irq(struct irq_desc *, struct msi_desc *, 90 const struct hw_interrupt_type *); 91 extern void teardown_msi_irq(int irq); 92 extern int msi_free_vector(struct msi_desc *entry); 93 extern int pci_restore_msi_state(struct pci_dev *pdev); 94 95 struct msi_desc { 96 struct msi_attrib { 97 __u8 type; /* {0: unused, 5h:MSI, 11h:MSI-X} */ 98 __u8 pos; /* Location of the MSI capability */ 99 __u8 maskbit : 1; /* mask/pending bit supported ? */ 100 __u8 is_64 : 1; /* Address size: 0=32bit 1=64bit */ 101 __u8 host_masked : 1; 102 __u8 guest_masked : 1; 103 __u16 entry_nr; /* specific enabled entry */ 104 } msi_attrib; 105 106 bool irte_initialized; 107 uint8_t gvec; /* guest vector. valid when pi_desc isn't NULL */ 108 const struct pi_desc *pi_desc; /* pointer to posted descriptor */ 109 110 struct list_head list; 111 112 union { 113 void __iomem *mask_base;/* va for the entry in mask table */ 114 struct { 115 unsigned int nvec;/* number of vectors */ 116 unsigned int mpos;/* location of mask register */ 117 } msi; 118 unsigned int hpet_id; /* HPET (dev is NULL) */ 119 }; 120 struct pci_dev *dev; 121 int irq; 122 int remap_index; /* index in interrupt remapping table */ 123 124 struct msi_msg msg; /* Last set MSI message */ 125 }; 126 127 /* 128 * Values stored into msi_desc.msi_attrib.pos for non-PCI devices 129 * (msi_desc.msi_attrib.type is zero): 130 */ 131 #define MSI_TYPE_UNKNOWN 0 132 #define MSI_TYPE_HPET 1 133 #define MSI_TYPE_IOMMU 2 134 135 int msi_maskable_irq(const struct msi_desc *); 136 int msi_free_irq(struct msi_desc *entry); 137 138 /* 139 * Assume the maximum number of hot plug slots supported by the system is about 140 * ten. The worstcase is that each of these slots is hot-added with a device, 141 * which has two MSI/MSI-X capable functions. To avoid any MSI-X driver, which 142 * attempts to request all available vectors, NR_HP_RESERVED_VECTORS is defined 143 * as below to ensure at least one message is assigned to each detected MSI/ 144 * MSI-X device function. 145 */ 146 #define NR_HP_RESERVED_VECTORS 20 147 148 #define msi_control_reg(base) (base + PCI_MSI_FLAGS) 149 #define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO) 150 #define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI) 151 #define msi_data_reg(base, is64bit) \ 152 ( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 ) 153 #define msi_mask_bits_reg(base, is64bit) \ 154 ( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4) 155 #define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE 156 #define multi_msi_capable(control) \ 157 (1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1)) 158 #define multi_msi_enable(control, num) \ 159 control |= (((fls(num) - 1) << 4) & PCI_MSI_FLAGS_QSIZE); 160 #define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT)) 161 #define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT)) 162 #define msi_enable(control, num) multi_msi_enable(control, num); \ 163 control |= PCI_MSI_FLAGS_ENABLE 164 165 #define msix_control_reg(base) (base + PCI_MSIX_FLAGS) 166 #define msix_table_offset_reg(base) (base + PCI_MSIX_TABLE) 167 #define msix_pba_offset_reg(base) (base + PCI_MSIX_PBA) 168 #define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE 169 #define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE 170 #define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1) 171 #define multi_msix_capable msix_table_size 172 #define msix_unmask(address) (address & ~PCI_MSIX_VECTOR_BITMASK) 173 #define msix_mask(address) (address | PCI_MSIX_VECTOR_BITMASK) 174 175 /* 176 * MSI Defined Data Structures 177 */ 178 179 struct __packed msg_data { 180 #if defined(__LITTLE_ENDIAN_BITFIELD) 181 __u32 vector : 8; 182 __u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */ 183 __u32 reserved_1 : 3; 184 __u32 level : 1; /* 0: deassert | 1: assert */ 185 __u32 trigger : 1; /* 0: edge | 1: level */ 186 __u32 reserved_2 : 16; 187 #elif defined(__BIG_ENDIAN_BITFIELD) 188 __u32 reserved_2 : 16; 189 __u32 trigger : 1; /* 0: edge | 1: level */ 190 __u32 level : 1; /* 0: deassert | 1: assert */ 191 __u32 reserved_1 : 3; 192 __u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */ 193 __u32 vector : 8; 194 #else 195 #error "Bitfield endianness not defined! Check your byteorder.h" 196 #endif 197 }; 198 199 struct __packed msg_address { 200 union { 201 struct { 202 #if defined(__LITTLE_ENDIAN_BITFIELD) 203 __u32 reserved_1 : 2; 204 __u32 dest_mode : 1; /*0:physic | 1:logic */ 205 __u32 redirection_hint: 1; /*0: dedicated CPU 206 1: lowest priority */ 207 __u32 reserved_2 : 4; 208 __u32 dest_id : 24; /* Destination ID */ 209 #elif defined(__BIG_ENDIAN_BITFIELD) 210 __u32 dest_id : 24; /* Destination ID */ 211 __u32 reserved_2 : 4; 212 __u32 redirection_hint: 1; /*0: dedicated CPU 213 1: lowest priority */ 214 __u32 dest_mode : 1; /*0:physic | 1:logic */ 215 __u32 reserved_1 : 2; 216 #else 217 #error "Bitfield endianness not defined! Check your byteorder.h" 218 #endif 219 }u; 220 __u32 value; 221 }lo_address; 222 __u32 hi_address; 223 }; 224 225 #define MAX_MSIX_TABLE_ENTRIES (PCI_MSIX_FLAGS_QSIZE + 1) 226 #define MAX_MSIX_TABLE_PAGES PFN_UP(MAX_MSIX_TABLE_ENTRIES * \ 227 PCI_MSIX_ENTRY_SIZE + \ 228 (~PCI_MSIX_BIRMASK & (PAGE_SIZE - 1))) 229 230 struct arch_msix { 231 unsigned int nr_entries, used_entries; 232 struct { 233 unsigned long first, last; 234 } table, pba; 235 int table_refcnt[MAX_MSIX_TABLE_PAGES]; 236 int table_idx[MAX_MSIX_TABLE_PAGES]; 237 spinlock_t table_lock; 238 bool host_maskall, guest_maskall; 239 domid_t warned; 240 }; 241 242 void early_msi_init(void); 243 void msi_compose_msg(unsigned vector, const cpumask_t *mask, 244 struct msi_msg *msg); 245 void __msi_set_enable(u16 seg, u8 bus, u8 slot, u8 func, int pos, int enable); 246 void mask_msi_irq(struct irq_desc *); 247 void unmask_msi_irq(struct irq_desc *); 248 void guest_mask_msi_irq(struct irq_desc *, bool mask); 249 void ack_nonmaskable_msi_irq(struct irq_desc *); 250 void end_nonmaskable_msi_irq(struct irq_desc *, u8 vector); 251 void set_msi_affinity(struct irq_desc *, const cpumask_t *); 252 253 #endif /* __ASM_MSI_H */ 254