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Searched refs:pci_conf_read32 (Results 1 – 15 of 15) sorted by relevance

/xen-4.10.0-shim-comet/xen/drivers/passthrough/vtd/
A Dquirks.c131 igd_mmio = pci_conf_read32(0, 0, IGD_DEV, 0, PCI_BASE_ADDRESS_1); in map_igd_reg()
133 igd_mmio += pci_conf_read32(0, 0, IGD_DEV, 0, PCI_BASE_ADDRESS_0); in map_igd_reg()
283 device = pci_conf_read32(0, bus, 20, 0, PCI_VENDOR_ID); in tylersburg_intremap_quirk()
299 ioh_id = pci_conf_read32(0, 0, IOH_DEV, 0, 0); in platform_quirks_init()
300 igd_id = pci_conf_read32(0, 0, IGD_DEV, 0, 0); in platform_quirks_init()
359 id = pci_conf_read32(0, 0, 0, 0, 0); in me_wifi_quirk()
363 if ( pci_conf_read32(0, 0, 3, 0, 0) == 0xffffffff ) in me_wifi_quirk()
387 if ( pci_conf_read32(0, 0, 22, 0, 0) == 0xffffffff ) in me_wifi_quirk()
442 val = pci_conf_read32(seg, bus, dev, func, 0x1AC); in pci_vtd_quirk()
501 val = pci_conf_read32(seg, bus, dev, func, 0x20c); in pci_vtd_quirk()
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/xen-4.10.0-shim-comet/xen/arch/x86/x86_64/
A Dmmconfig-shared.c92 pciexbar = pci_conf_read32(0, 0, 0, 0, 0x48); in pci_mmcfg_intel_945()
216 l = pci_conf_read32(0, bus, 0, 0, 0); in pci_mmcfg_nvidia_mcp55()
223 extcfg = pci_conf_read32(0, bus, 0, 0, extcfg_regnum); in pci_mmcfg_nvidia_mcp55()
242 l = pci_conf_read32(0, bus, 0, 0, 0); in pci_mmcfg_nvidia_mcp55()
249 extcfg = pci_conf_read32(0, bus, 0, 0, extcfg_regnum); in pci_mmcfg_nvidia_mcp55()
315 l = pci_conf_read32(0, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), 0); in pci_mmcfg_check_hostbridge()
A Dmmconf-fam10h.c55 id = pci_conf_read32(0, bus, slot, 0, PCI_VENDOR_ID); in get_fam10h_pci_mmconf_base()
86 val = pci_conf_read32(0, bus, slot, 1, 0x80 + (i << 3)); in get_fam10h_pci_mmconf_base()
91 val = pci_conf_read32(0, bus, slot, 1, 0x84 + (i << 3)); in get_fam10h_pci_mmconf_base()
A Dpci.c50 uint32_t pci_conf_read32( in pci_conf_read32() function
/xen-4.10.0-shim-comet/xen/drivers/pci/
A Dpci.c97 header = pci_conf_read32(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos); in pci_find_next_ext_capability()
113 header = pci_conf_read32(seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pos); in pci_find_next_ext_capability()
/xen-4.10.0-shim-comet/xen/arch/x86/
A Dmsi.c207 msg->address_lo = pci_conf_read32(seg, bus, slot, func, in read_msi_msg()
211 msg->address_hi = pci_conf_read32(seg, bus, slot, func, in read_msi_msg()
408 mask_bits = pci_conf_read32(seg, bus, slot, func, entry->msi.mpos); in msi_set_mask_bit()
478 return (pci_conf_read32(entry->dev->seg, entry->dev->bus, in msi_get_mask_bit()
737 maskbits = pci_conf_read32(seg, bus, slot, func, mpos); in msi_capability_init()
811 addr = pci_conf_read32(seg, bus, slot, func, base + bir * 4); in read_pci_mem_bar()
820 ((u64)pci_conf_read32(seg, bus, slot, func, in read_pci_mem_bar()
889 table_offset = pci_conf_read32(seg, bus, slot, func, in msix_capability_init()
936 pba_offset = pci_conf_read32(seg, bus, slot, func, in msix_capability_init()
A Dmm.c5539 igd_id = pci_conf_read32(0, 0, 2, 0, 0); in get_platform_badpages()
/xen-4.10.0-shim-comet/xen/drivers/char/
A Dehci-dbgp.c685 u32 class = pci_conf_read32(0, bus, slot, func, PCI_CLASS_REVISION); in __find_dbgp()
1009 u32 dword = pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func, 0x74); in nvidia_set_debug_port()
1042 cap = pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func, offset); in ehci_dbgp_bios_handoff()
1057 cap = pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func, offset); in ehci_dbgp_bios_handoff()
1310 debug_port = pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func, in ehci_dbgp_init_preirq()
1505 debug_port = pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func, in ehci_dbgp_init()
1517 dbgp->bar_val = bar_val = pci_conf_read32(0, dbgp->bus, dbgp->slot, in ehci_dbgp_init()
A Dns16550.c1053 bar = pci_conf_read32(0, b, d, f, in pci_uart_config()
1061 len = pci_conf_read32(0, b, d, f, PCI_BASE_ADDRESS_0 + bar_idx*4); in pci_uart_config()
1068 bar_64 = pci_conf_read32(0, b, d, f, in pci_uart_config()
1072 len_64 = pci_conf_read32(0, b, d, f, in pci_uart_config()
1090 len = pci_conf_read32(0, b, d, f, PCI_BASE_ADDRESS_0); in pci_uart_config()
/xen-4.10.0-shim-comet/xen/arch/x86/cpu/
A Damd.c417 nr_nodes = ((pci_conf_read32(0, 0, 0x18, 0x0, 0x60)>>4)&0x07)+1; in disable_c1_ramping()
638 l = pci_conf_read32(0, 0, 0x18, 0x3, 0x58); in init_amd()
639 h = pci_conf_read32(0, 0, 0x18, 0x3, 0x5c); in init_amd()
/xen-4.10.0-shim-comet/xen/drivers/passthrough/amd/
A Diommu_detect.c51 iommu->cap.header = pci_conf_read32(seg, bus, dev, func, cap_ptr); in get_iommu_capabilities()
A Diommu_init.c848 value = pci_conf_read32(iommu->seg, bus, dev, func, 0xf4); in amd_iommu_erratum_746_workaround()
1204 id = pci_conf_read32(0, bus, 0x14, 0, PCI_VENDOR_ID); in amd_sp5100_erratum28()
/xen-4.10.0-shim-comet/xen/arch/x86/oprofile/
A Dop_model_athlon.c463 id = pci_conf_read32(0, bus, dev, func, PCI_VENDOR_ID); in init_ibs_nmi()
474 value = pci_conf_read32(0, bus, dev, func, IBSCTL); in init_ibs_nmi()
/xen-4.10.0-shim-comet/xen/include/xen/
A Dpci.h142 uint32_t pci_conf_read32(
/xen-4.10.0-shim-comet/xen/drivers/passthrough/
A Dpci.c679 u32 bar = pci_conf_read32(seg, bus, slot, func, idx); in pci_add_device()
703 hi = pci_conf_read32(seg, bus, slot, func, idx + 4); in pci_add_device()
706 pdev->vf_rlen[i] = pci_conf_read32(seg, bus, slot, func, idx) & in pci_add_device()
711 pdev->vf_rlen[i] |= (u64)pci_conf_read32(seg, bus, in pci_add_device()
956 vendor = pci_conf_read32(seg, bus, dev, func, PCI_VENDOR_ID); in pci_device_detect()

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