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/xen-4.10.0-shim-comet/xen/arch/arm/arm32/
A Dhead.S86 mov r0, r0
143 add r0, r0, r10 /* Apply physical offset */
145 2: ldr r1, [r0]
157 mov r0, r7
191 add r0, r0, r10 /* Apply physical offset */
196 cmp r0, r1
206 mov r4, r0
208 mov r0, r4
365 orr r0, r0, #(SCTLR_M|SCTLR_C) /* Enable MMU and D-cache */
553 adr r0, 1f
[all …]
A Dproc-v7.S27 mrc CP32(r0, ACTLR)
28 orr r0, r0, #(ACTLR_CAXX_SMP) /* enable SMP bit */
29 mcr CP32(r0, ACTLR)
A Dentry.S17 push {r0-r12}; /* Save R0-R12 */ \
121 mov r0, sp; \
132 mov r0, sp; \
143 mov r0, sp; \
197 pop {r0-r12}
211 add ip, r0, #VCPU_arch_saved_context
A Ddebug.S33 early_uart_transmit r1, r0
A Ddomain.c11 C(r0,r0_usr); C(r1,r1_usr); C(r2,r2_usr); C(r3,r3_usr); \
/xen-4.10.0-shim-comet/xen/arch/arm/arm32/lib/
A Dbitops.h10 mov r0, r0, lsr #5
20 strex r0, r2, [r1]
21 cmp r0, #0
35 mov r0, r0, lsr #5
51 cmp r0, #0
52 movne r0, #1
63 and r2, r0, #31
64 mov r0, r0, lsr #5
91 mov r0, r0, lsr #5
94 mov r0, #1
[all …]
A Dmemzero.S23 strltb r2, [r0], #1 @ 1
24 strleb r2, [r0], #1 @ 1
25 strb r2, [r0], #1 @ 1
85 andgts ip, r0, #31
92 stmmiia r0!, {r4, r5}
94 strcs r2, [r0], #4
105 stmneia r0!, {r4-r7}
113 strne r2, [r0], #4 @ 1
119 strneb r2, [r0], #1 @ 1
120 strneb r2, [r0], #1 @ 1
[all …]
A Dlib1funcs.S211 cmp r0, r1
218 mov r0, r2
227 mov r0, r0, lsr r2
242 andeq r0, r0, r2
272 rsbmi r0, r0, #0
276 rsbmi r0, r0, #0
281 orreq r0, r0, #1
288 rsbmi r0, r0, #0
302 rsbmi r0, r0, #0 @ if negative make positive
307 andeq r0, r0, r2
[all …]
A Dfindbit.S30 THUMB( ldrb r3, [r0, r3] )
36 3: mov r0, r1 @ no free bits
51 THUMB( ldrb r3, [r0, r3] )
71 THUMB( ldrb r3, [r0, r3] )
92 THUMB( ldrb r3, [r0, r3] )
109 THUMB( ldrb r3, [r0, r3] )
176 rsb r0, r3, #0
177 and r3, r3, r0
180 add r0, r2, r3
190 mov r0, r2
[all …]
A Dmemmove.S29 subs ip, r0, r1
33 stmfd sp!, {r0, r4, lr}
35 add r0, r0, r2
38 ands ip, r0, #3
87 W(str) r3, [r0, #-4]!
88 W(str) r4, [r0, #-4]!
89 W(str) r5, [r0, #-4]!
90 W(str) r6, [r0, #-4]!
105 strcsb ip, [r0, #-1]
115 strb lr, [r0, #-1]!
[all …]
A Dcopy_template.S74 ands ip, r0, #3
84 CALGN( ands ip, r0, #31 )
136 str1w r0, r3, abort=20f
137 str1w r0, r4, abort=20f
138 str1w r0, r5, abort=20f
139 str1w r0, r6, abort=20f
140 str1w r0, r7, abort=20f
141 str1w r0, r8, abort=20f
142 str1w r0, lr, abort=20f
166 str1b r0, lr, abort=21f
[all …]
A Dmemchr.S19 ldrb r3, [r0], #1
22 sub r0, r0, #1
23 2: movne r0, #0
A Dstrchr.S20 1: ldrb r2, [r0], #1
25 movne r0, #0
26 subeq r0, r0, #1
A Dstrrchr.S18 1: ldrb r2, [r0], #1
20 subeq r3, r0, #1
23 mov r0, r3
A Dassembler.h109 stmdb sp!, {r0-r3, ip, lr}
111 ldmia sp!, {r0-r3, ip, lr}
121 stmdb sp!, {r0-r3, ip, lr}
123 ldmia sp!, {r0-r3, ip, lr}
205 mcr p15, 0, r0, c7, c5, 4
221 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
A Dlshrdi3.S31 #define ah r0
33 #define al r0
A Dmemset.S18 ands r3, r0, #3 @ 1 unaligned?
19 mov ip, r0 @ preserve r0 as return value
A Dmemcpy.S46 stmdb sp!, {r0, \reg1, \reg2}
50 ldmfd sp!, {r0, \reg1, \reg2}
A Ddiv64.S17 #define xh r0
22 #define xl r0
/xen-4.10.0-shim-comet/xen/include/asm-arm/
A Delf.h5 unsigned long r0; member
A Dregs.h51 #define return_reg(v) ((v)->arch.cpu_info->guest_cpu_user_regs.r0)
/xen-4.10.0-shim-comet/xen/include/asm-arm/arm32/
A Dprocessor.h12 uint32_t r0; member
77 #define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";"
/xen-4.10.0-shim-comet/xen/include/asm-arm/arm64/
A Dprocessor.h26 __DECL_REG(x0, r0/*_usr*/);
/xen-4.10.0-shim-comet/xen/arch/arm/
A Dtraps.c249 BUILD_BUG_ON(REGOFFS(r0) + 7*sizeof(register_t) != REGOFFS(r7)); in select_user_reg()
250 return &regs->r0 + reg; in select_user_reg()
807 regs->r0, regs->r1, regs->r2, regs->r3); in show_registers_32()
1464 #define HYPERCALL_RESULT_REG(r) (r)->r0
1465 #define HYPERCALL_ARG1(r) (r)->r0
1470 #define HYPERCALL_ARGS(r) (r)->r0, (r)->r1, (r)->r2, (r)->r3, (r)->r4
A Ddomain.c448 case 0: regs->r0 = arg; break; in hypercall_create_continuation()
458 rc = regs->r0; in hypercall_create_continuation()

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