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Searched defs:REG (Results 1 – 5 of 5) sorted by relevance

/arm-trusted-firmware-2.8.0/drivers/arm/gic/v3/
A Dgicv3_private.h28 #define BIT_NUM(REG, id) \ argument
37 #define GICD_OFFSET_8(REG, id) \ argument
42 #define GICD_OFFSET(REG, id) \ argument
55 #define GICD_OFFSET_8(REG, id) \ argument
58 #define GICD_OFFSET(REG, id) \ argument
61 #define GICD_OFFSET_64(REG, id) \ argument
69 #define GICD_READ(REG, base, id) \ argument
114 #define GICR_OFFSET_8(REG, id) \ argument
119 #define GICR_OFFSET(REG, id) \ argument
125 #define GICR_OFFSET_8(REG, id) \ argument
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A Dgicv3_main.c48 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ argument
58 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ argument
68 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ argument
79 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ argument
89 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) argument
90 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) argument
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/apusys/
A Dapupwr_clkctl_def.h71 #define apupwr_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
72 #define apupwr_writel_relax(VAL, REG) mmio_write_32_relax((uintptr_t)REG, VAL) argument
73 #define apupwr_readl(REG) mmio_read_32((uintptr_t)REG) argument
74 #define apupwr_clrbits(VAL, REG) mmio_clrbits_32((uintptr_t)REG, VAL) argument
75 #define apupwr_setbits(VAL, REG) mmio_setbits_32((uintptr_t)REG, VAL) argument
76 #define apupwr_clrsetbits(CLR_VAL, SET_VAL, REG) \ argument
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/apusys/
A Dmtk_apusys_apc_def.h85 #define apuapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
86 #define apuapc_readl(REG) mmio_read_32((uintptr_t)REG) argument
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/devapc/
A Ddevapc.h173 #define devapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
174 #define devapc_readl(REG) mmio_read_32((uintptr_t)REG) argument

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